专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07821243B2 DC/DC converter 有权
标题翻译： DC / DC转换器
公开(公告)号：US07821243B2
公开(公告)日：2010-10-26
申请号：US11624837
申请日：2007-01-19
申请人： Masaki Shiraishi , Takayuki Hashimoto , Noboru Akiyama
发明人： Masaki Shiraishi , Takayuki Hashimoto , Noboru Akiyama
IPC分类号： G05F1/595
CPC分类号： H02M1/08 , H01L24/48 , H01L24/49 , H01L2224/48137 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/12032 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H03K17/0822 , H03K17/165 , H03K17/166 , H03K17/6871 , H01L2924/00 , H01L2224/45099
摘要： In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
摘要翻译：在非隔离型DC / DC转换器中，从通过高侧MOSFET的主电路以外的部分施加驱动低侧MOSFET的栅极的低侧预驱动器的基准电位，低侧MOSFET，使得低侧MOSFET的源极与预驱动器之间的寄生电感增加，而不增加主电路中的寄生电感的和，并且低侧MOSFET的栅极的负电位驱动并且可以防止在不添加任何构件和改变驱动系统的情况下自启闭现象。

2. 发明授权

US07777346B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07777346B2
公开(公告)日：2010-08-17
申请号：US12345917
申请日：2008-12-30
申请人： Kensuke Ishikawa , Tatsuyuki Saito , Masanori Miyauchi , Toshio Saito , Hiroshi Ashihara
发明人： Kensuke Ishikawa , Tatsuyuki Saito , Masanori Miyauchi , Toshio Saito , Hiroshi Ashihara
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/2855 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
摘要翻译：在制造半导体集成电路器件时，在形成于半导体衬底上的第一级互连件上的层间绝缘膜中形成互连沟槽和接触孔，在沟槽和接触孔内部形成阻挡膜，使其膜厚度从孔的底部的中心朝向接触孔底部的侧壁增加，在阻挡膜上形成铜膜，并且通过抛光形成第二级互连和连接器部分（插塞）通过CMP。以这种方式，通过连接器部分（插头）从第二级互连件流向第一级互连件的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致，使得电流路径可以分散，并且电子的浓度不容易发生。

3. 发明申请

US20110281541A1 Reconfigurable Receiver Architectures 审中-公开
标题翻译：可重构接收机架构
公开(公告)号：US20110281541A1
公开(公告)日：2011-11-17
申请号：US13105633
申请日：2011-05-11
申请人： Jonathan Borremans
发明人： Jonathan Borremans
IPC分类号： H04B1/10
CPC分类号： H04B1/18
摘要： An adaptive front-end architecture for a receiver is disclosed. In one embodiment, the adaptive front-end architecture includes an input configured to receive an input signal and a linear low-noise amplifier connected to the input and configured to amplify the input signal to produce an amplified input signal. The adaptive front-end architecture further includes a first passive mixer arrangement configured to generate first a local oscillator signal and mix the first local oscillator signal with the amplified input signal to produce a first baseband output signal. The adaptive front-end architecture further includes a second passive mixer arrangement configured to generate a second local oscillator signal and mix the second local oscillator signal with the input signal to produce a second baseband output signal. The adaptive front-end architecture further includes a baseband impedance component configured to filter the first baseband signal and/or the second baseband signal using impedance translation.
摘要翻译：公开了一种用于接收机的自适应前端架构。在一个实施例中，自适应前端架构包括被配置为接收输入信号的输入端和连接到输入端并被配置为放大输入信号以产生放大输入信号的线性低噪声放大器。自适应前端架构还包括被配置为首先生成本地振荡器信号并将第一本地振荡器信号与放大的输入信号混合以产生第一基带输出信号的第一无源混频器装置。自适应前端架构还包括被配置为产生第二本地振荡器信号并将第二本地振荡器信号与输入信号混合以产生第二基带输出信号的第二无源混频器装置。自适应前端架构还包括基带阻抗分量，其被配置为使用阻抗平移来对第一基带信号和/或第二基带信号进行滤波。

4. 发明申请

US20110255694A1 ENCODING/DECODING CIRCUIT 有权
标题翻译：编码/解码电路
公开(公告)号：US20110255694A1
公开(公告)日：2011-10-20
申请号：US13172217
申请日：2011-06-29
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
摘要翻译：编码/解码操作部分包括编码/解码操作电路和用于迂回编码解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且迂回编码/解码操作电路以输出输入数据无变化。必须从选择器向键存储部分和初始化矢量存储部分提供一条线。利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症电路布局。

5. 发明授权

US08022542B2 Semiconductor device having improved metal wiring 有权
标题翻译：具有改进的金属布线的半导体器件
公开(公告)号：US08022542B2
公开(公告)日：2011-09-20
申请号：US11543794
申请日：2006-10-06
申请人： Kazumi Saitou
发明人： Kazumi Saitou
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76849 , H01L23/53266 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an interlayer insulating film, a tungsten film, a first barrier metal film, a second barrier metal film and a metal wiring film. The interlayer insulating film is formed on the semiconductor substrate, and has an opening. The tungsten film is embedded in the opening. The first barrier metal film is formed on the tungsten film and excludes a Ti film. The second barrier metal film is formed on the first barrier metal film and is a Ti-containing film. The metal wiring film is formed on the second barrier metal film.
摘要翻译：半导体器件包括半导体衬底，层间绝缘膜，钨膜，第一阻挡金属膜，第二阻挡金属膜和金属布线膜。层间绝缘膜形成在半导体基板上，并具有开口。钨膜嵌入开口。第一阻挡金属膜形成在钨膜上，不包括Ti膜。第二阻挡金属膜形成在第一阻挡金属膜上，并且是含Ti膜。金属布线膜形成在第二阻挡金属膜上。

6. 发明授权

US07972920B2 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device 有权
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及半导体器件和半导体器件的制造方法
公开(公告)号：US07972920B2
公开(公告)日：2011-07-05
申请号：US12700344
申请日：2010-02-04
申请人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L21/8244 , G11C11/40
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

7. 发明授权

US07897509B2 Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device 有权
标题翻译：半导体晶片及其制造方法以及制造半导体器件的方法
公开(公告)号：US07897509B2
公开(公告)日：2011-03-01
申请号：US12823913
申请日：2010-06-25
申请人： Naotaka Tanaka , Kenji Kanemitsu , Takafumi Kikuchi , Takashi Akazawa
发明人： Naotaka Tanaka , Kenji Kanemitsu , Takafumi Kikuchi , Takashi Akazawa
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/90 , H01L2224/0554 , H01L2224/05556 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13144 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2224/13099 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.
摘要翻译：一种半导体晶片，包括：在形成晶片的通孔电极的位置处形成的管状沟槽; 绝缘构件，其被埋置在所述沟槽内部和所述沟槽的上表面上; 形成在所述绝缘构件的上表面上的栅电极膜和金属膜; 形成在金属膜的上表面上的多层柱状布线孔; 以及通过多层柱状布线通孔与金属膜电连接形成的外部连接电极。以这种方式，在薄晶片和设备开发之后，不需要具有干法蚀刻的新工艺来形成通孔电极。此外，引入特定设计可以形成通孔电极，同时显着降低了各个工艺的难度。

8. 发明授权

US07786585B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07786585B2
公开(公告)日：2010-08-31
申请号：US12188591
申请日：2008-08-08
申请人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
发明人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/823871 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
摘要翻译：在具有多层埋地布线的半导体集成电路装置中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

9. 发明授权

US07782025B2 Semiconductor device and power supply device using the same 有权
标题翻译：半导体装置及使用该装置的电源装置
公开(公告)号：US07782025B2
公开(公告)日：2010-08-24
申请号：US12349106
申请日：2009-01-06
申请人： Takayuki Hashimoto , Nobuyoshi Matsuura , Masaki Shiraishi , Yukihiro Satou , Tetsuya Kawashima
发明人： Takayuki Hashimoto , Nobuyoshi Matsuura , Masaki Shiraishi , Yukihiro Satou , Tetsuya Kawashima
IPC分类号： G05F1/613
CPC分类号： H01L25/16 , H01L25/074 , H01L2224/05554 , H01L2224/0603 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/4903 , H01L2224/49175 , H01L2924/00014 , H01L2924/12032 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H02M3/1588 , Y02B70/1466 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.
摘要翻译：提供能够减小电感的半导体器件。在其中将整流MOSFET，换向MOSFET和驱动这些MOSFET的驱动IC安装在一个封装上的半导体器件中，整流MOSFET，金属板和换向MOSFET被层压。主电路的电流从封装的后表面流向其前表面。金属板通过封装中的布线连接到输出端子。引线键合用于连接驱动IC，整流MOSFET和换向MOSFET，所有端子都放置在同一平面上。因此，电感变小，电源损耗和尖峰电压也降低。

10. 发明授权

US07834420B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07834420B2
公开(公告)日：2010-11-16
申请号：US12335302
申请日：2008-12-15
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
摘要翻译：一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置来形成局部布线。此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式