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1. 发明申请

US20100053181A1 METHOD AND DEVICE OF PROCESSING VIDEO 审中-公开
标题翻译：处理视频的方法和设备
公开(公告)号：US20100053181A1
公开(公告)日：2010-03-04
申请号：US12202285
申请日：2008-08-31
申请人： Erik M. Schlanger , Brendan D. Donahe
发明人： Erik M. Schlanger , Brendan D. Donahe
IPC分类号： G09G5/39
CPC分类号： H04N19/426 , H04N19/176 , H04N19/42 , H04N19/61
摘要： A memory controller is disclosed that allocates local memory space to a set of macroblocks of a picture being processed. Information associated with a specific macroblock of the set of macroblocks is written to non-local memory when it is no longer needed to complete processing of a current row of macroblocks. When information associated with the specific macroblock is later needed to process a different row of macroblocks, the memory controller allocates local memory space to the specific macroblock and stores the previously saved information from non-local memory to the local memory.
摘要翻译：公开了一种存储器控制器，其将局部存储空间分配给被处理的图像的一组宏块。当宏块的当前行不再需要完成处理时，与该宏块集合的特定宏块相关联的信息被写入非本地存储器。当随后需要与特定宏块相关联的信息来处理不同行的宏块时，存储器控制器将特定宏块分配本地存储器空间，并将先前保存的非本地存储器信息存储到本地存储器中。

2. 发明授权

US07164860B1 Advanced multi-protocol optical transport network 失效
标题翻译：先进的多协议光传输网络
公开(公告)号：US07164860B1
公开(公告)日：2007-01-16
申请号：US10210750
申请日：2002-07-31
申请人： Paolo L. Narvaez , Gary S. Tse
发明人： Paolo L. Narvaez , Gary S. Tse
IPC分类号： H04J3/00
CPC分类号： H04J3/1664 , H04J14/02 , H04J2203/0046 , H04J2203/0085 , H04J2203/0089
摘要： A high-speed optical network includes according to the invention a housing having a plurality of slots for accommodating a number of line cards and an optional backplane facilitating communication between the line cards. The line cards include a client communication interface and a DWDM communication interface, for example, gigabit Ethernet interface, SONET interface or DWDM interface. Advantages of the invention include a high-speed network and network components that are capable of performing at a level consistent with optical network systems and which efficiently supports DWDM in a space-effective and cost-effective manner.
摘要翻译：高速光网络包括根据本发明的具有用于容纳多个线路卡的多个槽的壳体和便于线路卡之间的通信的可选背板。线卡包括客户端通信接口和DWDM通信接口，例如千兆以太网接口，SONET接口或DWDM接口。本发明的优点包括能够以与光网络系统一致的级别执行并且以空间有效和成本有效的方式有效地支持DWDM的高速网络和网络组件。

3. 发明申请

US20080320478A1 AGE MATRIX FOR QUEUE DISPATCH ORDER 失效
标题翻译：年龄排序的年龄矩阵
公开(公告)号：US20080320478A1
公开(公告)日：2008-12-25
申请号：US11830727
申请日：2007-07-30
申请人： Gaurav Singh , Srivatsan Srinivasan , Lintsung Wong
发明人： Gaurav Singh , Srivatsan Srinivasan , Lintsung Wong
IPC分类号： G06F9/46
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
摘要翻译：一种用于队列分配的装置。该装置的实施例包括调度顺序数据结构，位向量和队列控制器。调度订单数据结构对应于一个队列。调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。队列控制器与队列和调度订单数据结构接口。队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。

4. 发明申请

US20080270774A1 Universal branch identifier for invalidation of speculative instructions 有权
标题翻译：推测说明无效的通用分支标识符
公开(公告)号：US20080270774A1
公开(公告)日：2008-10-30
申请号：US11799293
申请日：2007-04-30
申请人： Gaurav Singh , Srivatsan Srinivasan , Ricardo Ramirez , Wei-Hsiang Chen , Hai Ngoc Nguyen
发明人： Gaurav Singh , Srivatsan Srinivasan , Ricardo Ramirez , Wei-Hsiang Chen , Hai Ngoc Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.
摘要翻译：投机分支预测系统。该系统的实施例包括分支预测逻辑，提取逻辑和分支识别逻辑。分支预测逻辑被配置为预测指令流中的分支的分支路径。提取逻辑耦合到分支预测逻辑。提取逻辑被配置为推测性地获取与预测的分支路径相对应的指令。分支识别逻辑耦合到分支预测逻辑和提取逻辑。分支识别逻辑被配置为使用通用分支标识格式使用分支标识符标记所推测的获取的指令。通用分支识别格式包括与预测分支路径相对应的比特位置处的比特值。

5. 发明申请

US20080062927A1 Delegating Network Processor Operations to Star Topology Serial Bus Interfaces 有权
标题翻译：将网络处理器操作委托给星形拓扑串行总线接口
公开(公告)号：US20080062927A1
公开(公告)日：2008-03-13
申请号：US11831887
申请日：2007-07-31
申请人： Julianne Zhu , David Hass
发明人： Julianne Zhu , David Hass
IPC分类号： H04Q7/00
CPC分类号： G06F13/4286 , G06F9/3851 , G06F9/3857 , G06F9/3867 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

6. 发明授权

US07072345B2 Programmable integrated circuit for use in a network switch 有权
公开(公告)号：US07072345B2
公开(公告)日：2006-07-04
申请号：US09939464
申请日：2001-08-24
申请人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/106 , H04L49/201 , H04L49/205 , H04L49/252 , H04L49/3009 , H04L49/506 , H04L49/557 , H04L49/60 , H04L49/606 , H04L2012/5651 , H04L2012/5667
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.

7. 发明申请

US20090006510A1 System and method for deflate processing within a compression engine 失效
标题翻译：压缩引擎内的放气处理系统和方法
公开(公告)号：US20090006510A1
公开(公告)日：2009-01-01
申请号：US11824501
申请日：2007-06-29
申请人： Robert William Laker , David T. Hass
发明人： Robert William Laker , David T. Hass
IPC分类号： G06F7/00
CPC分类号： H03M7/3086
摘要： An apparatus to implement a deflate process in a compression engine. An embodiment of the apparatus includes a hash table, a dictionary, comparison logic, and encoding logic. The hash table is configured to hash a plurality of characters of an input data stream to provide a hash address. The dictionary is configured to provide a plurality of distance values in parallel based on the hash address. The distance values are stored in the dictionary. The comparison logic is configured to identify a corresponding length for each matching distance value from the plurality of distance values. The encoding logic is configured to encode the longest length and the matching distance value as a portion of a LZ77 code stream.
摘要翻译：在压缩引擎中实现放气过程的装置。该装置的实施例包括哈希表，字典，比较逻辑和编码逻辑。散列表被配置为对输入数据流的多个字符进行散列以提供散列地址。字典被配置为基于散列地址并行地提供多个距离值。距离值存储在字典中。比较逻辑被配置为从多个距离值中识别每个匹配距离值的对应长度。编码逻辑被配置为将最长长度和匹配距离值编码为LZ77码流的一部分。

8. 发明申请

US20080209038A1 Methods and systems for optimizing placement on a clock signal distribution network 审中-公开
标题翻译：用于优化时钟信号分配网络上的布局的方法和系统
公开(公告)号：US20080209038A1
公开(公告)日：2008-08-28
申请号：US11710249
申请日：2007-02-23
申请人： Andrew J. Tufano
发明人： Andrew J. Tufano
IPC分类号： G06F1/12
CPC分类号： G06F17/5072 , G06F2217/62
摘要： Methods for optimizing an initial placement a number of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers are presented, the methods including: characterizing the number of features by a number of register groupings, the number of register groupings defined by similarity of corresponding local drivers, wherein each of the number of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and iteratively moving the number of register groupings in accordance with a number of exception based rules over an increasingly widening area of comparison to create an optimized placement of the number of features.
摘要翻译：用于优化在集成电路（IC）上的时钟信号分配网络上的多个特征的初始放置的方法，其中所述多个特征包括多个寄存器和对应的多个本地驱动器，所述方法包括：通过多个寄存器分组的特征数量，由对应的本地驱动器的相似度定义的寄存器组的数量，其中寄存器组的数量在初始放置中由时钟信号分配网络上的限定区域物理地界定; 并且在越来越宽的比较区域上根据多个基于异常的规则迭代地移动寄存器组的数量，以创建特征数量的优化放置。

9. 发明申请

US20070204130A1 Advanced processor translation lookaside buffer management in a multithreaded system 失效
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US20070204130A1
公开(公告)日：2007-08-30
申请号：US11704709
申请日：2007-02-08
申请人： David Hass , Basab Mukherjee
发明人： David Hass , Basab Mukherjee
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.
摘要翻译：提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作几种模式，其中每个TLB部分包括多个条目。

10. 发明授权

US07234019B1 Method and apparatus for implementing a search engine using an SRAM 有权
标题翻译：使用SRAM实现搜索引擎的方法和装置
公开(公告)号：US07234019B1
公开(公告)日：2007-06-19
申请号：US10735107
申请日：2003-12-12
申请人： Sophia W. Kao , Govind Malalur , Brian Hang Wai Yang
发明人： Sophia W. Kao , Govind Malalur , Brian Hang Wai Yang
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , Y10S707/99936
摘要： A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.
摘要翻译：一种搜索引擎系统，包括耦合到存储体选择信号的存储器组，用于接收构造的密钥和输入密钥掩码的掩码逻辑，以及用于提供被掩蔽的密钥，用于接收至少两个被掩蔽密钥的散列函数块，以及用于提供至少三个散列公开了用于接收散列函数输出的功能输出和多路复用器，并且用于提供存储体选择信号。此外，系统可以允许使用局部掩码字段来对构造的密钥进行本地掩蔽。散列函数可以是循环冗余码（CRC）类型函数。存储体可以被布置为条目的桶，并且可以被实现为标准静态随机存取存储器（SRAM）。此外，该系统可以被配置为以共享模式操作以共享散列函数输出或非共享模式，由此可以为存储体的特定部分指定哈希函数输出。

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