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1. 发明申请

US20050055510A1 Advanced processor translation lookaside buffer management in a multithreaded system 有权
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US20050055510A1
公开(公告)日：2005-03-10
申请号：US10898150
申请日：2004-07-23
申请人： David Hass , Basab Mukherjee
发明人： David Hass , Basab Mukherjee
IPC分类号： G06F12/08 , H04L12/56 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

2. 发明申请

US20070204130A1 Advanced processor translation lookaside buffer management in a multithreaded system 失效
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US20070204130A1
公开(公告)日：2007-08-30
申请号：US11704709
申请日：2007-02-08
申请人： David Hass , Basab Mukherjee
发明人： David Hass , Basab Mukherjee
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.
摘要翻译：提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作几种模式，其中每个TLB部分包括多个条目。

3. 发明申请

US20080216074A1 ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM 失效
标题翻译：高级处理器翻译在多个系统中预览缓冲区管理
公开(公告)号：US20080216074A1
公开(公告)日：2008-09-04
申请号：US11961910
申请日：2007-12-20
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F9/54 , G06F9/46 , G06F12/08 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个多线程处理器核心，每个处理器核心具有数据高速缓存和指令高速缓存。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

4. 发明申请

US20080140956A1 ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM 审中-公开
公开(公告)号：US20080140956A1
公开(公告)日：2008-06-12
申请号：US12018144
申请日：2008-01-22
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

5. 发明授权

US07509476B2 Advanced processor translation lookaside buffer management in a multithreaded system 失效
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US07509476B2
公开(公告)日：2009-03-24
申请号：US11704709
申请日：2007-02-08
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.
摘要翻译：提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作几种模式，其中每个TLB部分包括多个条目。

6. 发明授权

US07346757B2 Advanced processor translation lookaside buffer management in a multithreaded system 有权
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US07346757B2
公开(公告)日：2008-03-18
申请号：US10898150
申请日：2004-07-23
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

7. 发明申请

US20120030445A1 ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM 有权
标题翻译：高级处理器翻译在多个系统中预览缓冲区管理
公开(公告)号：US20120030445A1
公开(公告)日：2012-02-02
申请号：US13195785
申请日：2011-08-01
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

8. 发明授权

US09092360B2 Advanced processor translation lookaside buffer management in a multithreaded system 有权
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US09092360B2
公开(公告)日：2015-07-28
申请号：US13195785
申请日：2011-08-01
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/10 , H04L12/931 , G06F12/08
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

9. 发明授权

US07991977B2 Advanced processor translation lookaside buffer management in a multithreaded system 失效
标题翻译：多线程系统中的高级处理器转换后备缓冲区管理
公开(公告)号：US07991977B2
公开(公告)日：2011-08-02
申请号：US11961910
申请日：2007-12-20
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/00 , G06F15/173
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

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