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1. 发明授权

US4933572A Dual mode voltage reference circuit and method 失效
标题翻译：双模参考电压和方式
公开(公告)号：US4933572A
公开(公告)日：1990-06-12
申请号：US418908
申请日：1989-10-05
申请人： Douglas S. Smith , Derek F. Bowers
发明人： Douglas S. Smith , Derek F. Bowers
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.
摘要翻译：描述了一种电压参考电路，其能够仅使用两个引脚来提供具有微调能力的内部产生的电压或外部产生的电压。内部电压通过中断电路连接到输入/输出端子，也可以接收外部产生的电压。微调终端用于施加微调电压信号以调整内部产生的电压。要从内部电压转换为外部电压源，将中断电压施加到正常微调电压范围之外的微调端子。该中断电压使中断电路中断内部电压源和输入/输出端子之间的连接，使输出端子可用于外部电压源。

2. 发明授权

US4677369A CMOS temperature insensitive voltage reference 失效
标题翻译： CMOS温度不敏感电压基准
公开(公告)号：US4677369A
公开(公告)日：1987-06-30
申请号：US778444
申请日：1985-09-19
申请人： Derek F. Bowers , Ali Tasdighi
发明人： Derek F. Bowers , Ali Tasdighi
IPC分类号： H01L27/04 , G05F1/56 , G05F3/18 , H01L21/822 , H01L29/864 , H01L29/866 , H03K3/26 , G05F3/16 , H01L27/02 , H01L29/90
CPC分类号： G05F3/18 , Y10S323/907
摘要： A temperature insensitive voltage reference is described which can advantageously be implemented using standard CMOS processing techniques. A pair of parasitic bipolar transistors are coupled with appropriate resistors to produce a voltage with a temperature coefficient that is equal in value but of opposite polarity to a zener diode voltage-temperature coefficient. This voltage is then combined with a zener diode voltage to yield the desired output reference voltage.
摘要翻译：描述了温度不敏感的电压参考，其可以有利地使用标准CMOS处理技术来实现。一对寄生双极晶体管与适当的电阻器耦合以产生具有与齐纳二极管电压 - 温度系数相反的值但与极性相反的温度系数的电压。然后将该电压与齐纳二极管电压组合以产生所需的输出参考电压。

3. 发明授权

US4542349A Digital controlled amplifier 失效
标题翻译：数字控制放大器
公开(公告)号：US4542349A
公开(公告)日：1985-09-17
申请号：US578971
申请日：1984-02-10
申请人： Werner H. Hoeft
发明人： Werner H. Hoeft
IPC分类号： H03F1/30 , H03G3/00 , H03G3/02 , H03M1/74 , H03G3/20
CPC分类号： H03G3/001
摘要： A digital control amplifier is provided as a unitary monolithic device to control the transfer function of an analog signal in response to a digital control, such as from a digital computer. A current transfer cell is employed which uses an amplifier circuit having transistors of like polarity, and is capable of both attenuation and greater than unity amplification of an input analog signal. A digital-two-analog converter is integrated into the system and employs a series of current dividers which enables a common reference current to be used for each bit of the converter. A current reference circuit for the converter employs a band gap voltage regulator with a temperature compensation design that varies the control signal applied to the current transfer cell to compensate for temperature-induced variations in the output of the cell.
摘要翻译：提供数字控制放大器作为整体单片设备，以响应诸如数字计算机的数字控制来控制模拟信号的传递功能。使用电流传输单元，其使用具有相同极性的晶体管的放大器电路，并且能够衰减并且大于输入模拟信号的单位放大。数字双模转换器集成到系统中，并采用一系列电流分配器，使得可以对转换器的每个位使用公共参考电流。用于转换器的电流参考电路采用具有温度补偿设计的带隙电压调节器，其改变施加到电流传输单元的控制信号，以补偿温度引起的电池输出变化。

4. 发明授权

US4374335A Tuneable I.C. active integrator 失效
标题翻译：可调节的I.C. 主动积分器
公开(公告)号：US4374335A
公开(公告)日：1983-02-15
申请号：US151419
申请日：1980-05-19
申请人： Kiyoshi Fukahori , Yukio Nishikawa
发明人： Kiyoshi Fukahori , Yukio Nishikawa
IPC分类号： G06G7/186 , H03L7/099 , H03H11/12 , H03L7/08
CPC分类号： H03L7/0805 , G06G7/186 , H03L7/099 , H03B2200/0062
摘要： An I.C. integrator circuit is provided with an active tuneable element by which a precise integrator time constant can be established, despite variations in the values of individual circuit components. A plurality of integrator circuits are connected in an overall frequency responsive circuit, each integrator circuit having a input transconductance stage, an output integrating stage, and an adjustable intermediate conditioning stage, the latter stage preferably comprising a Gilbert multiplier circuit. The time constant of each integrator circuit is controlled by the conditioning stage, which in turn is under the control of a bias circuit common to all of the integrator circuits. A desired net frequency response characteristic can be achieved by simple adjustments to the common bias circuit, despite normal tolerances and variations among individual integrator circuits.The circuit is completely integrated, is capable of operating at audio as well as at higher frequency ranges, has a greater tuneable range than prior art devices, and is highly linear.
摘要翻译：一个I.C. 积分器电路提供有一个有源可调谐元件，通过该元件可以建立精确的积分器时间常数，尽管各个电路元件的值有变化。多个积分器电路连接在整个频率响应电路中，每个积分器电路具有输入跨导级，输出积分级和可调中间调节级，后级优选地包括吉尔伯特乘法器电路。每个积分器电路的时间常数由调节级控制，调节级又由所有积分器电路共用的偏置电路控制。尽管在各个积分器电路之间存在正常的公差和变化，但是可以通过对公共偏置电路的简单调整来实现期望的净频率响应特性。该电路是完全集成的，能够在音频以及更高的频率范围下工作，具有比现有技术的设备更大的可调整范围，并且是高度线性的。

5. 发明授权

US4285051A Low glitch current switch 失效
标题翻译：低毛刺电流开关
公开(公告)号：US4285051A
公开(公告)日：1981-08-18
申请号：US125912
申请日：1980-02-29
申请人： Paul R. Henneuse
发明人： Paul R. Henneuse
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： An improved analog track and hold circuit has a glitch-free output as the circuit switches between the tracking and the holding of an input analog signal. The circuit is of the type having a capacitor for storing an analog voltage, a transconductance amplifier for producing a charging current for the capacitor proportional to the analog voltage, a current switch for connecting and disconnecting the charging current for the capacitor, and an output circuit to buffer the capacitor voltage to the output. The improvement includes a diode array establishing first and second reference nodes across the capacitor. The diodes in the array clamp the first and second nodes to fixed incremental voltage values greater and lesser, respectively, than the capacitor voltage as the circuit tracks the analog voltage, and to fixed incremental voltage values lesser and greater, respectively, than the capacitor voltage, as the circuit holds the analog voltage. The nodes reverse their polarities by equal amounts during the switching of the circuit between the tracking and holding. In this manner, an equal and opposite voltage magnitude change is produced at each node during the switching interval, thereby preventing any net change in the capacitor voltage, and providing a glitch-free output. A special current switch gates currents through the diode array to effect the clamping.
摘要翻译：改进的模拟跟踪和保持电路具有无毛刺输出，因为电路在跟踪和保持输入模拟信号之间切换。该电路具有用于存储模拟电压的电容器，用于产生与模拟电压成比例的电容器的充电电流的跨导放大器，用于连接和断开电容器的充电电流的电流开关，以及输出电路将电容器电压缓冲到输出端。该改进包括在电容器上建立第一和第二参考节点的二极管阵列。阵列中的二极管分别将电容器电压跟踪模拟电压和固定的增量电压值分别比电容器电压更小和更大地固定在第一和第二节点处，使固定的增量电压值分别比电容器电压更大和更小。，因为电路保持模拟电压。在跟踪和保持之间的电路切换期间，节点反转其极性相等的量。以这种方式，在切换间隔期间在每个节点处产生相等且相反的电压幅度变化，从而防止电容器电压的任何净变化，并提供无毛刺输出。一个特殊的电流开关将通过二极管阵列的栅极电流来实现钳位。

6. 发明授权

US4088905A Self-adjusting compatibility circuit for digital to analog converter 失效
标题翻译：用于数模转换器的自适应兼容电路
公开(公告)号：US4088905A
公开(公告)日：1978-05-09
申请号：US768867
申请日：1977-02-15
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： H03M1/74 , H03K17/62 , H03K19/018 , H03M1/00 , H03K5/156 , H03K5/18 , H03K13/02
CPC分类号： H03K19/01831 , H03M1/0678
摘要： A circuit for interfacing a digital to analog converter with input signals from three different logic systems, whereby appropriate threshold switching signals compatible with each logic system are presented to the converter when the proper logic control signal is applied to the circuit. The first logic system is characterized by logic control signals within a first voltage range, and switching thresholds which differ from the logic control signals by a fixed increment; the second system by logic control signals within a second voltage range higher than the first range, and switching thresholds equal to a fixed proportion of the logic control signal; and the third system by a substantially constant switching threshold for a predetermined positive supply voltage level.
摘要翻译：用于将数模转换器与来自三个不同逻辑系统的输入信号进行接口的电路，由此当将适当的逻辑控制信号施加到电路时，将与每个逻辑系统兼容的适当阈值切换信号提供给转换器。第一逻辑系统的特征在于在第一电压范围内的逻辑控制信号，以及不同于逻辑控制信号的切换阈值一个固定的增量; 所述第二系统通过逻辑控制信号在高于所述第一范围的第二电压范围内，以及切换阈值等于所述逻辑控制信号的固定比例; 并且对于预定的正电源电压电平，第三系统通过基本上恒定的开关阈值。

7. 发明授权

US4928934A Positive retention chip carrier 失效
标题翻译：正保留芯片载体
公开(公告)号：US4928934A
公开(公告)日：1990-05-29
申请号：US386562
申请日：1989-07-27
申请人： William D. Morton, Jr.
发明人： William D. Morton, Jr.
IPC分类号： H05K7/10
CPC分类号： H05K7/1053
摘要： A carrier for an integrated circuit (IC) can has a plurality of low profile symmetrically distributed flexible arms extending from the carrier base with small hook projections for engaging a flange on the perimeter of the can. The low arm profile enables information to be printed on the side of the can while it is in the carrier. The symmetrical distribution of the flexible arms imparts an even load upon the can to prevent bending of the leads. The carrier base has round holes for receiving electrical leads projecting from the can to minimize the scraping of the leads during insertion and removal of the can from the carrier.
摘要翻译：用于集成电路（IC）的载体可以具有多个低轮廓对称分布的柔性臂，其从载体基部延伸，具有用于接合罐周边上的凸缘的小钩突起。低臂配置使得信息可以在罐体的载体上打印。柔性臂的对称分布在罐上施加均匀的载荷以防止引线弯曲。载体基座具有圆孔，用于接收从罐突出的电引线，以最小化在将载体从载体插入和移除期间引线的刮擦。

8. 发明授权

US4675561A FET output drive circuit with parasitic transistor inhibition 失效
标题翻译： FET输出驱动电路具有寄生晶体管抑制
公开(公告)号：US4675561A
公开(公告)日：1987-06-23
申请号：US798430
申请日：1985-11-15
申请人： Derek F. Bowers
发明人： Derek F. Bowers
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H03K17/687 , H03K17/12
CPC分类号： H01L27/0921 , H01L27/0218 , H03K2217/0027
摘要： A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads. The circuit thus sacrifices low output impedance for high input impedance and voltage swing during light output loading when output impedance is not very important, and sacrifices high voltage swing for high input impedance and low output impedance at heavy loads at which the impedance levels are more important than voltage swing.
摘要翻译： CMOS输出驱动电路具有用CMOS工艺实现的两个场效应晶体管（FET），其特征在于寄生双极晶体管。两个晶体管的背栅通过诸如通过在公共阱中形成器件而被连接在一起，并且第二FET的背栅也被连接以防止其相关联的寄生双极晶体管导通。静态负载被施加到两个FET，使得它们的电压在低输出负载期间是相当的，导致具有高输入阻抗和高输出电压摆幅的驱动电路。输出端子取自第一FET，其电压在相对高的输出负载下与第二FET不平衡，导通第一FET的寄生双极晶体管。这为驱动电路提供了期望的高输入阻抗，并且对于重输出负载而言具有低输出阻抗。因此，当输出阻抗不是非常重要时，电路因此牺牲了高输入阻抗和高输入阻抗的低输出阻抗，并且在阻抗水平更重要的情况下牺牲了高输入阻抗的高电压摆幅和低负载下的低输出阻抗比电压摆幅。

9. 发明授权

US4583051A Extended range amplifier circuit 失效
标题翻译：扩展扩展电路
公开(公告)号：US4583051A
公开(公告)日：1986-04-15
申请号：US668721
申请日：1984-11-06
申请人： Derek F. Bowers
发明人： Derek F. Bowers
IPC分类号： H03F1/42 , H03F1/32 , H03F3/34 , H03F3/343 , H03F3/347 , H03F3/04 , H03K17/00
CPC分类号： H03F1/32 , H03F3/3435
摘要： An output circuit amplifier has first and second stage amplifying transistors with an impedance circuit connected between the base of the first stage transistor and the collector-emitter circuit of the second stage transistor to draw current from the first stage transistor base, thereby keeping both transistors out of saturation. The impedance circuit establishes a voltage drop between the two transistors such that large output voltage swings are enabled at an output terminal connected to the second stage transistor. The collector-emitter circuit of the first stage transistor is connected directly to a positive voltage bus to avoid further saturation problems.
摘要翻译：输出电路放大器具有第一级放大晶体管和第二级放大晶体管，其阻抗电路连接在第一级晶体管的基极与第二级晶体管的集电极 - 发射极之间，以从第一级晶体管基极中抽出电流，从而保持两个晶体管出来的饱和度。阻抗电路在两个晶体管之间建立电压降，使得在连接到第二级晶体管的输出端子处使能大的输出电压摆幅。第一级晶体管的集电极 - 发射极电路直接连接到正电压母线，以避免进一步的饱和问题。

10. 发明授权

US4503381A Integrated circuit current mirror 失效
标题翻译：集成电路电流镜
公开(公告)号：US4503381A
公开(公告)日：1985-03-05
申请号：US472963
申请日：1983-03-07
申请人： Derek F. Bowers
发明人： Derek F. Bowers
IPC分类号： G05F3/26 , H03F3/34 , H03F3/343 , G05F3/16
CPC分类号： G05F3/265 , H03F3/343
摘要： An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.
摘要翻译：一种集成电流镜电路，其中补偿晶体管被添加到反射镜的每个级中以补偿镜电路中的其它晶体管的基底衬底漏电流并且使电路即使在高温和低电流水平下也能工作。每个补偿晶体管在其级中与其他晶体管匹配，并且其集电极 - 发射极电路连接在电压源端子和其他晶体管的公共基极连接之间。每个补偿晶体管的基极与电路的其余部分不连接，但是表现出在补偿方案中采用的基底漏极电流。

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