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1. 发明授权

US4374335A Tuneable I.C. active integrator 失效
标题翻译：可调节的I.C. 主动积分器
公开(公告)号：US4374335A
公开(公告)日：1983-02-15
申请号：US151419
申请日：1980-05-19
申请人： Kiyoshi Fukahori , Yukio Nishikawa
发明人： Kiyoshi Fukahori , Yukio Nishikawa
IPC分类号： G06G7/186 , H03L7/099 , H03H11/12 , H03L7/08
CPC分类号： H03L7/0805 , G06G7/186 , H03L7/099 , H03B2200/0062
摘要： An I.C. integrator circuit is provided with an active tuneable element by which a precise integrator time constant can be established, despite variations in the values of individual circuit components. A plurality of integrator circuits are connected in an overall frequency responsive circuit, each integrator circuit having a input transconductance stage, an output integrating stage, and an adjustable intermediate conditioning stage, the latter stage preferably comprising a Gilbert multiplier circuit. The time constant of each integrator circuit is controlled by the conditioning stage, which in turn is under the control of a bias circuit common to all of the integrator circuits. A desired net frequency response characteristic can be achieved by simple adjustments to the common bias circuit, despite normal tolerances and variations among individual integrator circuits.The circuit is completely integrated, is capable of operating at audio as well as at higher frequency ranges, has a greater tuneable range than prior art devices, and is highly linear.
摘要翻译：一个I.C. 积分器电路提供有一个有源可调谐元件，通过该元件可以建立精确的积分器时间常数，尽管各个电路元件的值有变化。多个积分器电路连接在整个频率响应电路中，每个积分器电路具有输入跨导级，输出积分级和可调中间调节级，后级优选地包括吉尔伯特乘法器电路。每个积分器电路的时间常数由调节级控制，调节级又由所有积分器电路共用的偏置电路控制。尽管在各个积分器电路之间存在正常的公差和变化，但是可以通过对公共偏置电路的简单调整来实现期望的净频率响应特性。该电路是完全集成的，能够在音频以及更高的频率范围下工作，具有比现有技术的设备更大的可调整范围，并且是高度线性的。

2. 发明授权

US08265174B2 Method and apparatus for detection of load impedance modulation in a transformer circuit 有权
标题翻译：用于检测变压器电路中负载阻抗调制的方法和装置
公开(公告)号：US08265174B2
公开(公告)日：2012-09-11
申请号：US12725307
申请日：2010-03-16
申请人： Kiyoshi Fukahori , Russell Hershbarger
发明人： Kiyoshi Fukahori , Russell Hershbarger
IPC分类号： H04B3/00
CPC分类号： H04L25/0266 , H01F27/42 , H01F2019/085 , H04L5/1423 , H04L25/0282 , H04L25/4904 , H04L25/4908
摘要： A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.
摘要翻译：提出了一种用于检测负载阻抗调制的方法和装置，作为从变压器的次级到初级侧的数据通信的结果。使用跨屏障通信的数据，对变压器势垒次级的负载阻抗进行差分调制。初级侧的检测电路将负载电流与初级侧的励磁电流隔离。负载电流随后在两个连续的曼彻斯特周期内积分，并将第一个曼彻斯特周期的积分值与第二个周期的积分值进行比较，从而恢复接收到的数据。

3. 发明授权

US06563655B1 Method and apparatus for failsafing and extending range for write precompensation 失效
标题翻译：用于写入预补偿的故障切换和扩展范围的方法和装置
公开(公告)号：US06563655B1
公开(公告)日：2003-05-13
申请号：US08650850
申请日：1996-05-20
申请人： Richard G. Yamasaki , Tomoaki Ohtsu , Kiyoshi Fukahori
发明人： Richard G. Yamasaki , Tomoaki Ohtsu , Kiyoshi Fukahori
IPC分类号： G11B509
CPC分类号： G11B20/10194
摘要： Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range of precompensation is extended beyond limits imposed by the duty cycle of the clock signal. Catastrophic failure of the write precompensation circuit is prevented by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The range of a write precompensation circuit is extended by ORing the clock and the clock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.
摘要翻译：可以防止写入预补偿电路发生灾难性故障，而不会将预补偿范围限制在较小的值，并且预补偿的范围延伸到由时钟信号的占空比施加的限制之外。通过将比较器的输入或输出与时钟的相反相位进行或运算来防止写入预补偿电路的灾难性故障。 180度延迟时钟强制任何将被遗漏的过渡。写入预补偿电路的范围通过将时钟和时钟延迟时间td来延长。结果的扩展占空比用于产生较长的预补偿延迟。还提供了一种技术来在宽范围的数据速率下保持恒定的占空比。

4. 发明授权

US4210830A High speed switching circuit 失效
标题翻译：高速开关电路
公开(公告)号：US4210830A
公开(公告)日：1980-07-01
申请号：US937510
申请日：1978-08-28
申请人： Kiyoshi Fukahori
发明人： Kiyoshi Fukahori
IPC分类号： H03K3/2885 , H03K5/153
CPC分类号： H03K3/2885
摘要： A voltage comparator is provided with a high speed output stage having positive feedback. The output stage uses two transistors, both in grounded emitter circuit configurations, and two current sources supplying current to two different nodes associated with the two transistors. One node is connected to the base of a first one of the two transistors and to the collector of the second transistor. The other node is at the junction of the base of the second transistor and a resistor connected to the collector of the first transistor. An input comparator circuit selectively diverts current from the base of the second transistor. When the current is diverted from the base of the second transistor, the first transistor is turned on and the second transistor is turned off, as its base is starved of any drive. When the input voltage changes so that the current is no longer diverted, current is supplied first through the resistor to the collector of the first transistor and then to the base of the second transistor. The voltage at the base rises rapidly to turn on the second transistor and at the same time the declining collector-to-emitter voltage of the second transistor reduces the base voltage at the first transistor so it quickly turns off. The circuit is compatible with Integrated Injection Logic (I.sup.2 L), and other logic systems.
摘要翻译：电压比较器具有正反馈的高速输出级。输出级使用两个晶体管，无论是在接地发射极电路配置中，还有两个电流源向两个与两个晶体管相关联的两个不同节点提供电流。一个节点连接到两个晶体管中的第一个晶体管的基极和第二晶体管的集电极。另一个节点在第二晶体管的基极和连接到第一晶体管的集电极的电阻的结点处。输入比较器电路选择性地从第二晶体管的基极分流电流。当电流从第二晶体管的基极转移时，第一晶体管导通，并且第二晶体管关断，因为其基极缺乏任何驱动。当输入电压变化使得电流不再转移时，电流首先通过电阻器被提供给第一晶体管的集电极，然后提供给第二晶体管的基极。基极上的电压迅速升高以导通第二晶体管，同时第二晶体管的集电极 - 发射极电压的下降降低了第一晶体管的基极电压，因此其快速关断。该电路与集成注入逻辑（I2L）和其他逻辑系统兼容。

5. 发明授权

US5432475A Method of offset voltage trim for automatic gain controls 失效
标题翻译：自动增益控制偏移电压调整方法
公开(公告)号：US5432475A
公开(公告)日：1995-07-11
申请号：US260065
申请日：1994-06-15
申请人： Kiyoshi Fukahori
发明人： Kiyoshi Fukahori
IPC分类号： H03F3/45 , H03G1/04 , H03G3/30
CPC分类号： H03G1/04 , H03F3/45479 , H03F2203/45022 , H03F2203/45048 , H03F2203/45051
摘要： A method for providing DC offset trim for automatic gain controls independent of temperature or gain. A DC trim current is added or subtracted from one side of the differential AGC circuit. The trim current balances the currents through the two halves of the differential circuit, eliminating DC offset at the AGC output. The trim current is derived from a current source that is dependent upon another current source that provides the current through the two halves of the differential circuit. Therefore, the trim current responds any changes in the current supplied to the differential AGC circuit. Thus, DC offset trim independent of temperature or gain, as well as reduction of the total harmonic distortion and direct DC coupling of signals between stages, is provided.
摘要翻译：提供独立于温度或增益的自动增益控制的直流偏移调整的方法。直流微调电流从差分AGC电路的一侧加或减。微调电流平衡差分电路两半的电流，消除了AGC输出端的直流偏移。微调电流来自电流源，该电流源取决于提供通过差分电路的两半的电流的另一电流源。因此，微调电流响应提供给差分AGC电路的电流的任何变化。因此，提供独立于温度或增益的DC偏移调整，以及降低总谐波失真和级之间的信号的直接DC耦合。

6. 发明授权

US4777453A Quadrature amplitude modulator using switched capacitor filter 失效
标题翻译：使用开关电容滤波器的正交幅度调制器
公开(公告)号：US4777453A
公开(公告)日：1988-10-11
申请号：US44883
申请日：1987-05-01
申请人： Paul Hurst , Kiyoshi Fukahori
发明人： Paul Hurst , Kiyoshi Fukahori
IPC分类号： H03C1/00 , H04L25/49 , H04L27/36 , H04L27/04
CPC分类号： H04L27/362 , H04L25/4919 , H04L27/36
摘要： A switched capacitor circuit implements a base band, finite impulse response filter (BBF) and balanced modulator with a single operational amplifier. The analog modulator has particular application in voice band modem applications and requires little or no microprocessor code space. Simplified sine and cosine functions are implemented in a pair of base band filters such that the output of only one base band filter is required at any one time. In this manner, a single operational amplifier may be utilized to implement the analog modulator/base band filter of the present invention. The use of switched capacitor technology and a single operational amplifier results in less silicon area dedicated to the analog modulator than for corresponding digital modulators.
摘要翻译：开关电容电路实现基带，有限脉冲响应滤波器（BBF）和具有单个运算放大器的平衡调制器。模拟调制器在语音频带调制解调器应用中具有特殊应用，并且需要很少或没有微处理器代码空间。简化的正弦和余弦功能在一对基带滤波器中实现，使得在任何一个时间只需要一个基带滤波器的输出。以这种方式，可以使用单个运算放大器来实现本发明的模拟调制器/基带滤波器。使用开关电容技术和单个运算放大器，相比于相应的数字调制器，导致模拟调制器专用的硅面积更少。

7. 发明申请

US20100239030A1 METHOD AND APPARATUS FOR DETECTION OF LOAD IMPEDANCE MODULATION IN A TRANSFORMER CIRCUIT 有权
标题翻译：用于检测变压器电路中负载阻抗调制的方法和装置
公开(公告)号：US20100239030A1
公开(公告)日：2010-09-23
申请号：US12725307
申请日：2010-03-16
申请人： Kiyoshi Fukahori , Russell Hershbarger
发明人： Kiyoshi Fukahori , Russell Hershbarger
IPC分类号： H04B3/00
CPC分类号： H04L25/0266 , H01F27/42 , H01F2019/085 , H04L5/1423 , H04L25/0282 , H04L25/4904 , H04L25/4908
摘要： A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.
摘要翻译：提出了一种用于检测负载阻抗调制的方法和装置，作为从变压器的次级到初级侧的数据通信的结果。使用跨屏障通信的数据，对变压器势垒次级的负载阻抗进行差分调制。初级侧的检测电路将负载电流与初级侧的励磁电流隔离。负载电流随后在两个连续的曼彻斯特周期内积分，并将第一个曼彻斯特周期的积分值与第二个周期的积分值进行比较，从而恢复接收到的数据。

8. 发明授权

US07408996B2 Method and apparatus for synchronization of data in a transformer circuit 有权
标题翻译：变压器电路中数据同步的方法和装置
公开(公告)号：US07408996B2
公开(公告)日：2008-08-05
申请号：US11476923
申请日：2006-06-27
申请人： Russell Hershbarger , Kiyoshi Fukahori
发明人： Russell Hershbarger , Kiyoshi Fukahori
IPC分类号： H04B3/00
CPC分类号： H04B3/548 , H04B2203/5408 , H04J7/00 , H04L5/14 , H04L7/033 , H04L7/046 , H04L25/0266 , H04L25/0284 , H04L25/4904 , H04M11/066
摘要： A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.
摘要翻译：介绍了一种使次级侧与变压器电路的初级侧同步的方法和装置。首先使用主要由数据脉冲和反相功率脉冲组成的前导码来获得用于和设置锁相环的参数。例如，可以使用边沿触发单触发电路从前导码生成参考时钟，直到检测到锁定。一旦锁相环锁定到时钟上，则初级和次级之间的正常通信开始。在正常通信中，位于次级的锁相环使用来自发射信号的有效曼彻斯特边缘保持同相。

9. 发明申请

US20070009052A1 Method and apparatus for synchronization of data in a transformer circuit 有权
标题翻译：变压器电路中数据同步的方法和装置
公开(公告)号：US20070009052A1
公开(公告)日：2007-01-11
申请号：US11476923
申请日：2006-06-27
申请人： Russell Hershbarger , Kiyoshi Fukahori
发明人： Russell Hershbarger , Kiyoshi Fukahori
IPC分类号： H04B3/00
CPC分类号： H04B3/548 , H04B2203/5408 , H04J7/00 , H04L5/14 , H04L7/033 , H04L7/046 , H04L25/0266 , H04L25/0284 , H04L25/4904 , H04M11/066
摘要： A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses is used initially to obtain the parameters for and to set up a phase locked loop. For example, an edge-triggered one-shot circuit can be used to generate a reference clock from the preamble until lock is detected. Once the phase lock loop locks onto the clock, normal communication between the primary and secondary commences. The phase lock loop, which is in the secondary, is kept in phase during normal communication using valid Manchester edges from the transmit signal.
摘要翻译：介绍了一种使次级侧与变压器电路的初级侧同步的方法和装置。首先使用主要由数据脉冲和反相功率脉冲组成的前导码来获得用于和设置锁相环的参数。例如，可以使用边沿触发单触发电路从前导码生成参考时钟，直到检测到锁定。一旦锁相环锁定到时钟上，则初级和次级之间的正常通信开始。在正常通信中，位于次级的锁相环使用来自发射信号的有效曼彻斯特边缘保持同相。

10. 发明授权

US06178538B1 Interleaved analog metric calculator 失效
标题翻译：交错模拟量度计算器
公开(公告)号：US06178538B1
公开(公告)日：2001-01-23
申请号：US09021766
申请日：1998-02-11
申请人： Kiyoshi Fukahori
发明人： Kiyoshi Fukahori
IPC分类号： H03M1341
CPC分类号： H03M13/6343 , H03M13/27 , H03M13/4107 , H03M13/6502
摘要： A metric calculator is disclosed having an interleaved structure for increasing the time during which metrics can be calculated by circuit components. A first interleave samples voltage of the received signal during a first phase and a second interleave samples voltage of the received signal during an opposite phase. The interleaved architecture calculates and updates metrics and decisions based on these metrics at code rate, without requiring completion of all ACS computations in one code period.
摘要翻译：公开了一种度量计算器，其具有用于增加电路组件可以计算度量的时间的交织结构。在第一阶段期间，接收信号的第一交错采样电压和在相反阶段期间接收信号的第二交织采样电压。交织的体系结构以码率计算和更新基于这些度量的度量和决策，而不需要在一个代码周期内完成所有的ACS计算。

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