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1. 发明授权

US06417762B1 Power line communication system using anti-resonance isolation and virtual earth ground signaling 失效
标题翻译：电力线通信系统采用反共振隔离和虚拟接地信号
公开(公告)号：US06417762B1
公开(公告)日：2002-07-09
申请号：US09822695
申请日：2001-03-30
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： H04M1104
CPC分类号： H04B3/54 , H04B2203/5425 , H04B2203/5441 , H04B2203/5445 , H04B2203/5483
摘要： A method and system for transmitting and receiving high-frequency electrical communication signals over a previously installed building power line network is presented, in which minimal or no electrical modifications of the power line network are required. A high-frequency signal is impressed between earth ground/neutral and building ground power lines that are tied into a common ground bar at a service panel. The high-frequency signal isolates the earth ground line/neutral and building ground lines by creating an “anti-resonant” condition. Since building ground is required by electrical safety codes to be present at all electrical outlets within the building, the carrier signals can be transmitted and received from any electrical outlet within the building. The high-frequency communication signals are not impressed on load carrying wires of the power line network, and are consequently not subject to the bandwidth, noise and high-voltage problems associated with other power line communication methods.
摘要翻译：提出了一种用于在先前安装的建筑物电力线网络上发送和接收高频电气通信信号的方法和系统，其中需要电力线网络的最小的或不需要电气修改。在接地/空载和建筑物接地电源线之间施加高频信号，这些线路被连接到维修面板上的公共接地棒中。高频信号通过产生“反谐振”状态来隔离地线/中性线和建筑物地线。由于建筑地面需要电气安全规范存在于建筑物内的所有电源插座上，因此载波信号可以从建筑物内的任何电源插座传输和接收。高频通信信号不会对电力线网络的承载线施加影响，因此不会受到与其他电力线通信方法相关的带宽，噪声和高电压问题的影响。

2. 发明授权

US06816096B2 Response-based analog-to-digital conversion apparatus and method 失效
公开(公告)号：US06816096B2
公开(公告)日：2004-11-09
申请号：US10421129
申请日：2003-04-23
申请人： Donald T. Comer , Darren S. Korth
发明人： Donald T. Comer , Darren S. Korth
IPC分类号： H03M120
CPC分类号： H03M1/206 , H03M1/365
摘要： An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.

3. 发明授权

US4088905A Self-adjusting compatibility circuit for digital to analog converter 失效
标题翻译：用于数模转换器的自适应兼容电路
公开(公告)号：US4088905A
公开(公告)日：1978-05-09
申请号：US768867
申请日：1977-02-15
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： H03M1/74 , H03K17/62 , H03K19/018 , H03M1/00 , H03K5/156 , H03K5/18 , H03K13/02
CPC分类号： H03K19/01831 , H03M1/0678
摘要： A circuit for interfacing a digital to analog converter with input signals from three different logic systems, whereby appropriate threshold switching signals compatible with each logic system are presented to the converter when the proper logic control signal is applied to the circuit. The first logic system is characterized by logic control signals within a first voltage range, and switching thresholds which differ from the logic control signals by a fixed increment; the second system by logic control signals within a second voltage range higher than the first range, and switching thresholds equal to a fixed proportion of the logic control signal; and the third system by a substantially constant switching threshold for a predetermined positive supply voltage level.
摘要翻译：用于将数模转换器与来自三个不同逻辑系统的输入信号进行接口的电路，由此当将适当的逻辑控制信号施加到电路时，将与每个逻辑系统兼容的适当阈值切换信号提供给转换器。第一逻辑系统的特征在于在第一电压范围内的逻辑控制信号，以及不同于逻辑控制信号的切换阈值一个固定的增量; 所述第二系统通过逻辑控制信号在高于所述第一范围的第二电压范围内，以及切换阈值等于所述逻辑控制信号的固定比例; 并且对于预定的正电源电压电平，第三系统通过基本上恒定的开关阈值。

4. 发明授权

US06943626B2 Wideband precision fixed-gain amplifier architecture, apparatus, and method 失效
标题翻译：宽带精密固定增益放大器架构，装置和方法
公开(公告)号：US06943626B2
公开(公告)日：2005-09-13
申请号：US10741642
申请日：2003-12-19
申请人： Donald T. Comer , Brent R. Carlton
发明人： Donald T. Comer , Brent R. Carlton
IPC分类号： H03F3/343 , H03F3/45 , H03F3/50 , H03G3/30 , H03G5/16
CPC分类号： H03F3/45475 , H03F3/3432 , H03F3/50 , H03F2200/36 , H03G3/30
摘要： An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.
摘要翻译：公开了一种用于提高固定增益放大器的增益精度和带宽的装置和方法，同时提供许多应用中所需的高带宽和性能。具有相对精确增益的固定增益放大器在特定架构中连接在一起，以进一步增加任何独立运行的放大器的增益精度和带宽。由于放大器的配置，各放大器的绝对增益误差基本上被消除，所以总电路的增益误差大大降低。公开的架构在需要非常精确的增益的许多高速，高带宽的应用中是有用的，同时避免了使用反馈来实现增益稳定性的放大器引起的带宽的减少。

5. 发明授权

US06927713B2 Response-based analog-to-digital conversion apparatus and method 失效
标题翻译：基于响应的模数转换装置和方法
公开(公告)号：US06927713B2
公开(公告)日：2005-08-09
申请号：US10826239
申请日：2004-04-16
申请人： Donald T. Comer , Darren S. Korth
发明人： Donald T. Comer , Darren S. Korth
IPC分类号： H03M1/20 , H03M1/36
CPC分类号： H03M1/206 , H03M1/365
摘要： An apparatus and method for increasing the resolution of analog-to-digital conversion devices and systems is described. The described apparatus and method operate without significantly increasing the complexity or conversion time of conventional analog-to-digital conversion architectures. The improved resolution is accomplished by detecting the time-dependent response characteristics of comparators used within an analog-to-digital converter. The detected response characteristics, such as the response pattern or the response time, are used to estimate the overdrive voltage on the comparator of interest and to thereby provide additional bits to the analog-to-digital conversion process. In those applications where the response characteristics affect the settling characteristics of the converter output bits, additional resolution may be attained by detecting the settling characteristics, such as the settling pattern or settling time, of the converter output bits, particularly the least significant bit.
摘要翻译：描述了用于增加模数转换装置和系统的分辨率的装置和方法。所描述的装置和方法操作而不显着增加常规模数转换架构的复杂性或转换时间。通过检测在模数转换器内使用的比较器的时间依赖性响应特性来实现改进的分辨率。检测到的响应特性，例如响应模式或响应时间，用于估计感兴趣的比较器上的过驱动电压，从而为模数转换过程提供额外的位。在响应特性影响转换器输出位的稳定特性的那些应用中，通过检测转换器输出位，特别是最低有效位的稳定特性，如稳定模式或建立时间，可以获得额外的分辨率。

6. 发明授权

US4118699A Digital to analog converter with binary and binary coded decimal modes 失效
标题翻译：具有二进制和二进制编码十进制模式的数模转换器
公开(公告)号：US4118699A
公开(公告)日：1978-10-03
申请号：US768326
申请日：1977-02-14
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： H03M1/68 , H03M1/00 , H03M1/74 , H03K13/05
CPC分类号： H03M1/1014 , H03M1/745
摘要： A digital to analog converter with bit circuits arranged in binary order, in which a supplemental current circuit is added to selected bit circuits to enable convenient and efficient conversion from binary to BCD operation. Supplemental BCD currents are controlled by a bias circuit which automatically increases the BCD bit circuit bias to a level at which the full-scale BCD output current is substantially equal to the full-scale binary output current.
摘要翻译：具有以二进制顺序布置的位电路的数模转换器，其中补充电流电路被添加到所选择的位电路以使得能够从二进制到BCD操作的方便和有效的转换。补充BCD电流由偏置电路控制，偏置电路将BCD位电路偏置自动增加到满量程BCD输出电流基本上等于满量程二进制输出电流的电平。

7. 发明授权

US5798502A Temperature controlled substrate for VLSI construction having minimal parasitic feedback 失效
标题翻译：用于具有最小寄生反馈的VLSI结构的温度控制衬底
公开(公告)号：US5798502A
公开(公告)日：1998-08-25
申请号：US644234
申请日：1996-05-10
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： G05D23/19 , H05B1/02
CPC分类号： G05D23/1913 , Y10T307/951
摘要： A closed loop control system for controlling the temperature of a heated substrate is presented. In the preferred embodiment, the closed loop control system is implemented substantially or completely on a single substrate. The closed loop control system comprises means to reduce or eliminate parasitic feedback in the control system. In one aspect of the present invention, the mechanism for reducing the effects of parasitic feedback comprises a mechanism to prevent minority carriers from collecting around the base of the temperature sensing device. The mechanism for preventing minority carriers from collecting around the base of the temperature sensing device can be one or more guard rings which attract the minority carriers and prevent them from collecting around the base of the temperature sensor. In another aspect of the present invention, the mechanism for reducing the effects of parasitic feedback can be a sample and hold circuit which approximates the theoretically ideal sample and hold circuit in order to present a substantially open circuit to the parasitic feedback.
摘要翻译：提出了一种用于控制加热衬底温度的闭环控制系统。在优选实施例中，闭环控制系统基本上或完全地在单个基板上实现。闭环控制系统包括减少或消除控制系统中的寄生反馈的装置。在本发明的一个方面，用于减少寄生反馈的影响的机构包括防止少数载流子围绕温度感测装置的底部收集的机构。用于防止少数载体收集在温度感测装置底部的机构可以是一个或多个保护环，其吸引少数载体并防止其聚集在温度传感器的基部周围。在本发明的另一方面，用于减小寄生反馈效应的机制可以是近似于理论上理想的采样和保持电路的采样保持电路，以便向寄生反馈提供基本上开路的电路。

8. 发明授权

US4138671A Selectable trimming circuit for use with a digital to analog converter 失效
标题翻译：可选择的微调电路，用于数模转换器
公开(公告)号：US4138671A
公开(公告)日：1979-02-06
申请号：US768328
申请日：1977-02-14
申请人： Donald T. Comer , Daniel J. Dooley , John A. Schoeff
发明人： Donald T. Comer , Daniel J. Dooley , John A. Schoeff
IPC分类号： H03M1/10 , H01L21/822 , H01L27/04 , H03M1/00 , H03K13/02
CPC分类号： H03M1/72 , H03M1/447
摘要： The outputs of individual stages in a digital to analog converter are each trimmed by independent circuitry which includes a plurality of transistors connected to a common output terminal, the physical dimensions of each transistor being scaled in proportion to desired levels of current flow, and selectable switches connected in circuit with each of the transistors. Selectable switches are actuable to produce an output trimming current of a desired magnitude, which current is used to correct the untrimmed stage output. The invention includes circuitry for controlling the polarity of the trimming current relative to the stage, and for selectively expanding or contracting the trimming range to optimize the trimming currents for the particular characteristics of the converter. A favorable balance between trimming accuracy and the area occupied by the trimming circuitry is attained by the use of both emitter-scaled and multicollector transistors in the trimming circuits.
摘要翻译：数模转换器中的各个级的输出各自由独立的电路进行修整，该独立电路包括连接到公共输出端的多个晶体管，每个晶体管的物理尺寸与所需电流水平成比例地缩放，以及可选开关与每个晶体管连接在一起。可选择的开关可致动以产生期望幅度的输出微调电流，该电流用于校正未调整的级输出。本发明包括用于控制相对于平台的微调电流的极性的电路，以及用于选择性地扩展或收缩微调范围以优化转换器的特定特性的微调电流。通过在修整电路中使用发射极尺寸和多极晶体管来实现微调精度与微调电路占据面积之间的平衡。

9. 发明授权

US4131884A Trimming control circuit for a digital to analog converter 失效
标题翻译：微调控制电路用于数模转换器
公开(公告)号：US4131884A
公开(公告)日：1978-12-26
申请号：US768327
申请日：1977-02-14
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： H03M1/10 , H01L21/822 , H01L27/04 , H03M1/00 , H03K13/02
CPC分类号： H03M1/662
摘要： Novel apparatus is described for controlling the application of circuit adjustment signals to an electrical circuit device. The same device leads are used in an operating mode with input signals in a first range, and in an adjustment mode with input signals in a second range, the two ranges being mutually exclusive.An exemplary embodiment is directed toward trimming a digital to analog converter. A plurality of trimming elements are provided with an equal number of two-terminal actuating devices, which are arranged in a matrix such that each pair of terminals is connected in circuit with a unique pair of input leads. The devices actuate their associated trimming elements in response to the application of actuating signals, exceeding a threshold level greater than the level of the binary input signals, to their respective lead pairs. The leads are thereby capable of a dual mode operation, with one mode for normal converter operation and the other mode for setting up desired trim circuits.
摘要翻译：描述了用于控制电路调整信号到电路装置的应用的新型装置。在具有第一范围的输入信号的操作模式中使用相同的器件引线，并且在具有在第二范围内的输入信号的调整模式中，两个范围是相互排斥的。

10. 发明授权

US5714902A Polynomial function generation circuit 失效
标题翻译：多项式函数生成电路
公开(公告)号：US5714902A
公开(公告)日：1998-02-03
申请号：US565389
申请日：1995-11-30
申请人： Donald T. Comer
发明人： Donald T. Comer
IPC分类号： G05F3/22 , G06F7/556
CPC分类号： G06G7/20 , G05F3/22
摘要： An electrical circuit for generating a polynomial function in response to a linear input signal is disclosed. The circuit in one embodiment comprises a primary and a secondary current mirror, with the collector or source of the secondary current mirror connected in common with the input signal of the primary current mirror. The output signal of the electrical circuit is taken at the mirrored current source terminal of the first current mirror. The primary and secondary current mirrors are biased to at least initially respond exponentially to the linear input signal. Each then transitions into the more linear, resistor-dominated range. The primary current mirror is enabled at a predetermined cut-in level, such that an upward curving exponential response function is generated in response thereto. The second current mirror being conducting at a later level of the input signal, but increases more quickly than the primary current mirror so as to gradually deplete the primary current mirror and cause the output signal to transition into a downward sloping exponential function at a predetermined transition point and at a predetermined peak signal amplitude. The output signal then gradually declines to a predetermined cut-out level, where it reaches zero. The circuit can be constructed using BJT or MOS devices and a single transistor can be used in place of the second current mirror. Tuning can be achieved with fusible link tuning resistors and with multiple emitter transistors, as well as with multiple output devices on the primary current mirror, which are digitally controlled for selecting the peak output signal level during operation.
摘要翻译：公开了一种用于响应于线性输入信号产生多项式函数的电路。一个实施例中的电路包括初级和次级电流镜，其中二次电流镜的集电极或源与主电流镜的输入信号共同连接。电路的输出信号在第一电流镜的镜像电流源端。初级和次级电流镜被偏置以至少初始地响应于线性输入信号的指数。然后每个转换成更线性的，以电阻为主的范围。初级电流镜在预定的切入电平使能，使得响应于此产生向上的弯曲指数响应函数。第二电流镜在输入信号的较后电平上导通，但是比初级电流镜更快地增加，以便逐渐消耗初级电流镜，并使输出信号在预定转换时转变成向下倾斜的指数函数点和预定的峰值信号幅度。然后，输出信号逐渐下降到预定的切出电平，其中它达到零。可以使用BJT或MOS器件构建电路，并且可以使用单个晶体管代替第二电流镜。可以使用可熔链路调谐电阻和多个发射极晶体管以及主电流镜上的多个输出器件实现调谐，数字控制可在运行期间选择峰值输出信号电平。

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