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1. 发明授权

US06965524B2 Non-volatile static random access memory 失效
标题翻译：非易失性静态随机存取存储器
公开(公告)号：US06965524B2
公开(公告)日：2005-11-15
申请号：US10394415
申请日：2003-03-19
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C14/00 , G11C16/0441
摘要： In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein. If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
摘要翻译：根据本发明，存储单元包括非易失性器件和SRAM单元。 SRAM单元包括第一和第二MOS晶体管。非易失性器件是SRAM单元的负载。如果第二SRAM单元和第二非易失性设备被布置在其中，则存储单元可以适于差分地操作。如果这样适应，SRAM单元和/或非易失性器件在编程时存储和提供补充数据。非易失性器件在编程之前被擦除。非易失性器件的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在SRAM中的数据被加载到非易失性设备中。电源恢复后，存储在非易失性器件中的数据在SRAM单元中恢复。数据的差分读取和拧紧减少了非易失性器件的过擦除。

2. 发明授权

US06965145B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06965145B2
公开(公告)日：2005-11-15
申请号：US10394417
申请日：2003-03-19
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： G11C14/00 , H01L29/792
CPC分类号： G11C14/00
摘要： A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.
摘要翻译：非易失性存储器件（以下可替代地称为器件）包括沿器件沟道长度的第一部分延伸的导向栅极和沿器件沟道长度的第二部分延伸的控制栅极。通道长度的第一和第二部分不重叠。在通道区域上方覆盖衬底的引导栅极与通过氧化物层形成器件的半导体衬底绝缘。也在通道区域上方覆盖衬底的控制栅极通过氧化物 - 氮化物 - 氧化物层与衬底绝缘。该器件包括源极端子，漏极端子，引导栅极端子，控制栅极端子和耦合到其中形成器件的半导体衬底的衬底端子。

3. 发明申请

US20060007772A1 Non-volatile memory device 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20060007772A1
公开(公告)日：2006-01-12
申请号：US11189548
申请日：2005-07-25
申请人： Kyu Choi
发明人： Kyu Choi
IPC分类号： G11C8/02
CPC分类号： G11C14/00
摘要： A non-volatile memory device includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The channel region under the guiding gate has a doping concentration greater than the doping concentration of the substrate. The remaining portion of the channel region has a doping concentration greater than the doping concentration of the substrate but less than the doping concentration of the channel region under the guiding gate. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer.
摘要翻译：非易失性存储器件包括沿器件沟道长度的第一部分延伸的引导门和沿设备通道长度的第二部分延伸的控制栅极。通道长度的第一和第二部分不重叠。在通道区域上方覆盖衬底的引导栅极与通过氧化物层形成器件的半导体衬底绝缘。引导栅极下方的沟道区域的掺杂浓度大于衬底的掺杂浓度。沟道区的剩余部分的掺杂浓度大于衬底的掺杂浓度，但是小于引导栅下的沟道区的掺杂浓度。也在通道区域上方覆盖衬底的控制栅极通过氧化物 - 氮化物 - 氧化物层与衬底绝缘。

4. 发明申请

US20040016947A1 Non-volatile dynamic random access memory 失效
标题翻译：非易失性动态随机存取存储器
公开(公告)号：US20040016947A1
公开(公告)日：2004-01-29
申请号：US10394407
申请日：2003-03-19
申请人： O2IC, Inc.
发明人： Kyu Hyun Choi
IPC分类号： H01L027/108 , H01L029/76
CPC分类号： G11C14/00
摘要： In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.
摘要翻译：根据本发明，存储单元包括非易失性器件和DRAM单元。 DRAM单元还包括MOS晶体管和电容器。非易失性器件包括可以部分重叠的控制栅极区域和引导栅极区域。非易失性器件在被编程之前被擦除。非易失性装置的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在DRAM中的数据被加载到非易失性设备中。在电源恢复之后，存储在非易失性装置中的数据在DRAM单元中恢复。

5. 发明申请

US20030179630A1 Non-volatile static random access memory 失效
标题翻译：非易失性静态随机存取存储器
公开(公告)号：US20030179630A1
公开(公告)日：2003-09-25
申请号：US10394415
申请日：2003-03-19
申请人： O2IC, Inc.
发明人： Kyu Hyun Choi
IPC分类号： G11C007/00
CPC分类号： G11C14/00 , G11C16/0441
摘要： In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
摘要翻译：根据本发明，存储单元包括非易失性器件和SRAM单元。 SRAM单元包括第一和第二MOS晶体管。非易失性器件是SRAM单元的负载。如果第二SRAM单元和第二非易失性器件被设置在其中，则存储器单元可以适于差分地工作。如果这样适应的话，SRAM单元和/或非易失性器件在被编程时存储和提供补充数据。非易失性器件在编程之前被擦除。非易失性器件的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在SRAM中的数据被加载到非易失性设备中。电源恢复后，存储在非易失性器件中的数据在SRAM单元中恢复。数据的差分读取和拧紧减少了非易失性器件的过擦除。

6. 发明授权

US07186612B2 Non-volatile DRAM and a method of making thereof 失效
标题翻译：非易失性DRAM及其制造方法
公开(公告)号：US07186612B2
公开(公告)日：2007-03-06
申请号：US10819596
申请日：2004-04-06
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L21/8234
CPC分类号： H01L27/108 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.
摘要翻译：形成非易失性DRAM的方法部分地包括在第一介电层上方形成第一多晶硅层以形成非易失性DRAM的非易失性器件的控制栅极; 形成与所述第一多晶硅层相邻的侧壁间隔物; 形成第二氧化物层; 在所述第二氧化物层上形成第二多晶硅层，在所述体区中形成轻掺杂区域; 在所述体区域上方形成第二间隔物，形成所述非易失性器件的源极和漏极区域以及所述非易失性DRAM的所述MOS晶体管; 在所述轻掺杂区域的部分上形成第三多晶硅层以形成多晶硅着陆焊盘; 在所述多晶硅着陆焊盘上形成第三电介质层; 以及在第三介电层上形成第四多晶硅层。

7. 发明授权

US06954377B2 Non-volatile differential dynamic random access memory 失效
标题翻译：非易失性差分动态随机存取存储器
公开(公告)号：US06954377B2
公开(公告)日：2005-10-11
申请号：US10394496
申请日：2003-03-19
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
摘要翻译：根据本发明，存储单元包括一对非易失性器件和一对DRAM单元，每个DRAM单元与不同的非易失性器件相关联。每个DRAM单元还包括一个MOS晶体管，一个电容器。 DRAM单元及其相关的非易失性器件在编程时存储和供应补充数据时工作差异。非易失性器件在编程之前被擦除。非易失性器件的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在DRAM中的数据被加载到非易失性设备中。在电源恢复之后，存储在非易失性设备中的数据在DRAM单元中恢复。数据的差分读取和拧紧减少了非易失性器件的过擦除。

8. 发明申请

US20050170586A1 Method of manufacturing non-volatile DRAM 审中-公开
标题翻译：制造非易失性DRAM的方法
公开(公告)号：US20050170586A1
公开(公告)日：2005-08-04
申请号：US10820189
申请日：2004-04-06
申请人： Kyu Choi
发明人： Kyu Choi
IPC分类号： G11C11/34 , G11C11/405 , G11C14/00 , G11C16/04 , H01L21/8239 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： G11C16/0425 , G11C11/405 , G11C14/00 , G11C14/0018 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10894
摘要： A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device disposed in the non-volatile DRAM, forming sidewall spacers adjacent the first polysilicon layer, forming a second polysilicon layer that forms a guiding gate of the non-volatile device disposed in the non-volatile DRAM and a gate of an MOS transistor disposed in the non-volatile DRAM, delivering first implants to the body region to form lightly doped areas in the body region, delivering second implants to the body region to define source and drain regions, forming second sidewall spacers above the body region to define regions receiving lightly dopes implants and to define a conducting region of a capacitor disposed in the non-volatile DRAM.
摘要翻译：形成非易失性DRAM的方法部分地包括在第一介电层上形成第一多晶硅层以形成设置在非易失性DRAM中的非易失性器件的控制栅极，形成邻近第一多晶硅的侧壁间隔物形成第二多晶硅层，其形成设置在非易失性DRAM中的非易失性器件的引导栅极和设置在非易失性DRAM中的MOS晶体管的栅极，将第一植入物递送到身体区域以形成轻微的在身体区域中的掺杂区域，将第二植入物递送到身体区域以限定源极和漏极区域，在身体区域上方形成第二侧壁间隔，以限定接收轻度掺杂植入物的区域，并且限定设置在非区域中的电容器的导电区域，易失性DRAM。

9. 发明申请

US20050161718A1 Non-volatile DRAM and a method of making thereof 失效
标题翻译：非易失性DRAM及其制造方法
公开(公告)号：US20050161718A1
公开(公告)日：2005-07-28
申请号：US10819596
申请日：2004-04-06
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115
CPC分类号： H01L27/108 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.
摘要翻译：形成非易失性DRAM的方法部分地包括在第一介电层上方形成第一多晶硅层以形成非易失性DRAM的非易失性器件的控制栅极; 形成与所述第一多晶硅层相邻的侧壁间隔物; 形成第二氧化物层; 在所述第二氧化物层上形成第二多晶硅层，在所述体区中形成轻掺杂区域; 在所述体区域上方形成第二间隔物，形成所述非易失性器件的源极和漏极区域以及所述非易失性DRAM的所述MOS晶体管; 在所述轻掺杂区域的部分上形成第三多晶硅层以形成多晶硅着陆焊盘; 在所述多晶硅着陆焊盘上形成第三电介质层; 以及在第三介电层上形成第四多晶硅层。

10. 发明申请

US20070242514A1 NAND-structured nonvolatile memory cell 审中-公开
标题翻译： NAND结构的非易失性存储单元
公开(公告)号：US20070242514A1
公开(公告)日：2007-10-18
申请号：US11373818
申请日：2006-03-10
申请人： David Choi , Kyu Choi
发明人： David Choi , Kyu Choi
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.
摘要翻译：耦合到NAND闪速存储器阵列的位线的多个NAND快闪存储器单元部分地包括耦合到耦合到多个单元的第二端子的第一端子和高掺杂漏极区域的高掺杂源极区域。每个NAND存储器单元部分地包括适于接收电压的第一栅极层和第二栅极层。 NAND闪存单元的第二栅极层彼此连接。

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