专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07232717B1 Method of manufacturing non-volatile DRAM 失效
标题翻译：制造非易失性DRAM的方法
公开(公告)号：US07232717B1
公开(公告)日：2007-06-19
申请号：US10447675
申请日：2003-05-28
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： H01L21/8244
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/11521
摘要： A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.
摘要翻译：形成非挥发性DRAM的方法部分包括：形成在半导体衬底中的两个沟槽隔离区之间形成p阱和n阱，形成设置在非易失性DRAM中的非易失性器件的多晶硅控制栅极，在本体区域的部分和邻近所述第一控制栅极之上形成第一氧化物隔离层，在体区上方形成不同厚度的栅极氧化物层，形成非易失性器件的引导栅极和相关联的栅极晶体管，形成非易失性器件的LDD注入区和相关联的栅极晶体管，形成非易失性器件的源极/漏极区域和相关联的栅极 - 晶体管，在介电层的多晶硅引导栅极上沉积介电层非易失性器件和相关联的闸门晶体管的多晶硅栅极，形成多晶硅着陆焊盘，以及形成限定非挥发物的电容器板的多晶硅垂直壁 e DRAM电容。

2. 发明授权

US06965145B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06965145B2
公开(公告)日：2005-11-15
申请号：US10394417
申请日：2003-03-19
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： G11C14/00 , H01L29/792
CPC分类号： G11C14/00
摘要： A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.
摘要翻译：非易失性存储器件（以下可替代地称为器件）包括沿器件沟道长度的第一部分延伸的导向栅极和沿器件沟道长度的第二部分延伸的控制栅极。通道长度的第一和第二部分不重叠。在通道区域上方覆盖衬底的引导栅极与通过氧化物层形成器件的半导体衬底绝缘。也在通道区域上方覆盖衬底的控制栅极通过氧化物 - 氮化物 - 氧化物层与衬底绝缘。该器件包括源极端子，漏极端子，引导栅极端子，控制栅极端子和耦合到其中形成器件的半导体衬底的衬底端子。

3. 发明授权

US06514819B1 High capacity stacked DRAM device and process for making a smaller geometry 失效
标题翻译：高容量堆叠DRAM器件和制造较小几何形状的工艺
公开(公告)号：US06514819B1
公开(公告)日：2003-02-04
申请号：US09258596
申请日：1999-02-26
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000A and small spaces down to 700 Å. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 Å comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material. Portions of the product material which are not protected by the masking material are removed to leave a desired width of product material corresponding to the width of the masking material. The corresponding process can be used to form spacings of corresponding dimensions.
摘要翻译：在不牺牲存储电容器值的情况下，获得具有100％的理论单元布局效率和高达4吉比特DRAM的密度的DRAM。这种成就通过在布局中引入着陆垫并获得低至1000A的窄宽度和低至700的小空间来实现。 DRAM具有主动隔离，字线，杯形垂直电容器壁和位线。用于形成具有这种窄宽度，窄壁和在800范围内的小空间的小尺寸的方法包括将成形材料沉积在产品材料的表面上。通过使用光刻技术通过RIE蚀刻去除部分成形材料。掩模材料层沉积在成形材料和产品材料上方，掩模材料层具有与产品材料的所需期望宽度相关的厚度。掩蔽材料通过垂直RIE去除直到成型材料暴露，留下预定宽度的掩模材料。去除未被掩蔽材料保护的产品材料的部分以留下与掩模材料的宽度相对应的所需产品材料宽度。相应的过程可用于形成相应尺寸的间距。

4. 再颁专利

USRE36490E Power and signal line bussing method for memory devices 失效
标题翻译：用于存储器件的电源和信号线总线方法
公开(公告)号：USRE36490E
公开(公告)日：2000-01-11
申请号：US886107
申请日：1997-06-30
申请人： Sang Ki Hwang , Tae Sung Jung , Kyu Hyun Choi
发明人： Sang Ki Hwang , Tae Sung Jung , Kyu Hyun Choi
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C11/34 , G11C11/401 , H01L21/822 , H01L27/04 , H01L27/10 , G11C13/00
CPC分类号： G11C5/025 , G11C5/14
摘要： A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.
摘要翻译：具有位于存储单元阵列之间的电路的存储单元器件包括到存储单元阵列正上方形成的电路的电源和地线。电源线和接地线平行并且位于相邻的交替图案中，使得电力线位于邻近另一电力线等的接地线附近。在电路上传送信号的信号线也直接形成在存储单元阵列上方。

5. 发明申请

US20050136592A1 METHOD OF MANUFACTURING SELF-ALIGNED NON-VOLATILE MEMORY DEVICE 失效
标题翻译：制造自对准非易失性存储器件的方法
公开(公告)号：US20050136592A1
公开(公告)日：2005-06-23
申请号：US10746907
申请日：2003-12-23
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric, a first polysilicon gate, and a second dielectric layer, respectively, above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, removing the second polysilicon layer and the layers below it that are exposed in a via formed using a mask, thereby forming self-aligned source/drain regions.
摘要翻译：一种形成自对准非易失性装置的方法，部分包括形成沟槽隔离区域，在沟槽隔离之间形成阱，在第一阱之上形成第二阱，在第一部分的第一部分上方形成第一氧化物层所述第二阱分别在所述第一多晶硅层上方形成第一电介质，第一多晶硅栅极和第二电介质层，在所述主体区域的上方形成与所述第一多晶硅层相邻的第一间隔物，在所述第一多晶硅层的上方形成第二氧化物层所述第二阱的第二部分未被所述第一间隔物覆盖，在所述第二氧化物层上方形成第二多晶硅栅极层，所述第一间隔物和所述第二电介质层的一部分，去除所述第二多晶硅层和暴露于其中的所述第二多晶硅层在使用掩模形成的通孔中，从而形成自对准的源/漏区。

6. 发明授权

US06798008B2 Non-volatile dynamic random access memory 失效
公开(公告)号：US06798008B2
公开(公告)日：2004-09-28
申请号：US10394407
申请日：2003-03-19
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L27108
CPC分类号： G11C14/00
摘要： In accordance with the present invention, a memory cell includes a non-volatile device and a DRAM cell. The DRAM cell further includes an MOS transistor and a capacitor. The non-volatile device include a control gate region and a guiding gate region that may partially overlap. The non-volatile device is erased prior to being programmed. Programming of the non-volatile device may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM is loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile device is restored in the DRAM cell.

7. 发明授权

US5946566A Method of making a smaller geometry high capacity stacked DRAM device 失效
标题翻译：制造较小几何大容量堆叠DRAM器件的方法
公开(公告)号：US5946566A
公开(公告)日：1999-08-31
申请号：US609846
申请日：1996-03-01
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000 .ANG. and small spaces down to 700 .ANG.. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 .ANG. comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material. Portions of the product material which are not protected by the masking material are removed to leave a desired width of product material corresponding to the width of the masking material. The corresponding process can be used to form spacings of corresponding dimensions.
摘要翻译：在不牺牲存储电容器值的情况下，获得具有100％的理论单元布局效率和高达4吉比特DRAM的密度的DRAM。这种成就是通过在布局中引入着陆垫并获得窄至1000个ANGSTROM和低至700安培的小空间来实现的。 DRAM具有主动隔离，字线，杯形垂直电容器壁和位线。用于形成具有窄窄度，窄壁和小范围的小尺寸的小尺寸的方法800 ANGSTROM包括将成形材料沉积在产品材料的表面上。通过使用光刻技术通过RIE蚀刻去除部分成形材料。掩模材料层沉积在成形材料和产品材料上方，掩模材料层具有与产品材料的所需期望宽度相关的厚度。掩蔽材料通过垂直RIE去除直到成型材料暴露，留下预定宽度的掩模材料。去除未被掩蔽材料保护的产品材料的部分以留下与掩模材料的宽度相对应的所需产品材料宽度。相应的过程可用于形成相应尺寸的间距。

8. 发明申请

US20100200065A1 Photovoltaic Cell and Fabrication Method Thereof 审中-公开
标题翻译：光伏电池及其制造方法
公开(公告)号：US20100200065A1
公开(公告)日：2010-08-12
申请号：US12704967
申请日：2010-02-12
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/06 , H01L31/02363 , H01L31/03529 , H01L31/0547 , H01L31/0682 , H01L31/18 , Y02E10/52 , Y02E10/547
摘要： The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions.
摘要翻译：本发明的结构及其制造方法提供了将光能转换为电能的光伏电池结构。根据一个实施例，柱形光伏电池结构包括彼此紧密定位的柱状阵列，以利用光的波状特性和颗粒状特性，以增强光伏电池的能量转换效率。根据一个实施例，结合自对准P / P +结的柱形光伏电池结构使得能够通过自对准P / P +结捕获在电池结构顶表面附近产生的孔。

9. 发明授权

US07186612B2 Non-volatile DRAM and a method of making thereof 失效
标题翻译：非易失性DRAM及其制造方法
公开(公告)号：US07186612B2
公开(公告)日：2007-03-06
申请号：US10819596
申请日：2004-04-06
申请人： Kyu Hyun Choi
发明人： Kyu Hyun Choi
IPC分类号： H01L21/8234
CPC分类号： H01L27/108 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.
摘要翻译：形成非易失性DRAM的方法部分地包括在第一介电层上方形成第一多晶硅层以形成非易失性DRAM的非易失性器件的控制栅极; 形成与所述第一多晶硅层相邻的侧壁间隔物; 形成第二氧化物层; 在所述第二氧化物层上形成第二多晶硅层，在所述体区中形成轻掺杂区域; 在所述体区域上方形成第二间隔物，形成所述非易失性器件的源极和漏极区域以及所述非易失性DRAM的所述MOS晶体管; 在所述轻掺杂区域的部分上形成第三多晶硅层以形成多晶硅着陆焊盘; 在所述多晶硅着陆焊盘上形成第三电介质层; 以及在第三介电层上形成第四多晶硅层。

10. 发明授权

US06954377B2 Non-volatile differential dynamic random access memory 失效
标题翻译：非易失性差分动态随机存取存储器
公开(公告)号：US06954377B2
公开(公告)日：2005-10-11
申请号：US10394496
申请日：2003-03-19
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
摘要翻译：根据本发明，存储单元包括一对非易失性器件和一对DRAM单元，每个DRAM单元与不同的非易失性器件相关联。每个DRAM单元还包括一个MOS晶体管，一个电容器。 DRAM单元及其相关的非易失性器件在编程时存储和供应补充数据时工作差异。非易失性器件在编程之前被擦除。非易失性器件的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在DRAM中的数据被加载到非易失性设备中。在电源恢复之后，存储在非易失性设备中的数据在DRAM单元中恢复。数据的差分读取和拧紧减少了非易失性器件的过擦除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式