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1. 发明授权

US5773990A Integrated circuit test power supply 失效
标题翻译：集成电路测试电源
公开(公告)号：US5773990A
公开(公告)日：1998-06-30
申请号：US536206
申请日：1995-09-29
申请人： Jan B. Wilstrup , Stanley Peter Mros
发明人： Jan B. Wilstrup , Stanley Peter Mros
IPC分类号： G01R31/30 , G01R31/319 , G01R31/3193 , G01R15/12
CPC分类号： G01R31/3004 , G01R31/3008 , G01R31/31924 , G01R31/3193
摘要： A power supply for testing an integrated circuit includes a source voltage input terminal for receiving an input voltage. The power supply serves as both a DUT active power supply and an IDDQ measurement circuit, without the need for switching between separate DUT active power supply and IDDQ measurement circuits. In one embodiment, a current source output driver includes a diode across a current sensing resistor inside a feedback loop. This minimizes VDD changes when the DUT demands transient current, such as when loading IDDQ test vectors. Moreover, with decreased transient changes in VDD, dielectric absorption effects of a decoupling capacitor are reduced.
摘要翻译：用于测试集成电路的电源包括用于接收输入电压的源极电压输入端子。电源既可用作DUT有源电源，也可用作IDDQ测量电路，无需在单独的DUT有源电源和IDDQ测量电路之间切换。在一个实施例中，电流源输出驱动器包括反馈回路内的电流检测电阻器两端的二极管。当DUT需要瞬态电流时，例如当加载IDDQ测试矢量时，这可以最大限度地减少VDD变化。此外，随着VDD瞬变的减小，去耦电容的介电吸收效应降低。

2. 发明授权

US4779221A Timing signal generator 失效
标题翻译：定时信号发生器
公开(公告)号：US4779221A
公开(公告)日：1988-10-18
申请号：US8212
申请日：1987-01-28
申请人： Paul D. Magliocco , Steven R. Bristow
发明人： Paul D. Magliocco , Steven R. Bristow
IPC分类号： G06F11/22 , G01R31/319 , G06F1/04 , G06F1/06 , H03K5/135 , G06F9/00
CPC分类号： G01R31/31922 , H03K5/135
摘要： A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.
摘要翻译：提供了一种独特的定时系统，其允许用户编程具有来自固定频率时钟的可变周期和边缘的定时事件，并且具有大于固定参考频率的分辨率的分辨率。固有昂贵，不准确，需要重复校准的延迟元件被最小化。

3. 发明授权

US5917331A Integrated circuit test method and structure 失效
标题翻译：集成电路测试方法和结构
公开(公告)号：US5917331A
公开(公告)日：1999-06-29
申请号：US546751
申请日：1995-10-23
申请人： Thomas Walkley Persons
发明人： Thomas Walkley Persons
IPC分类号： G01R31/30 , G01R31/3193 , G01R31/28
CPC分类号： G01R31/3004 , G01R31/3193
摘要： A power supply for testing an integrated circuit includes a source voltage input terminal for receiving an input voltage. A plurality of switches are coupled in parallel to the input terminal, where each of the switches is coupled to an associated resistor. Each resistor, in turn, is coupled to an output terminal that is connected to the device under test (DUT). A soft switch is connected to both the input terminal and output terminal, where the soft switch is configured to condition the output terminal voltage when one of the switches is opened or closed. The soft switch quickly stabilizes the output voltage and reduces transients in the VDUT output signal.
摘要翻译：用于测试集成电路的电源包括用于接收输入电压的源极电压输入端子。多个开关并联耦合到输入端，其中每个开关耦合到相关联的电阻器。每个电阻又连接到连接到被测器件（DUT）的输出端子。软开关连接到输入端子和输出端子，其中软开关被配置为在其中一个开关打开或关闭时调节输出端电压。软开关可快速稳定输出电压，并降低VDUT输出信号的瞬变。

4. 发明授权

US4809221A Timing signal generator 失效
标题翻译：定时信号发生器
公开(公告)号：US4809221A
公开(公告)日：1989-02-28
申请号：US186331
申请日：1988-04-26
申请人： Paul D. Magliocco , Steven R. Bristow
发明人： Paul D. Magliocco , Steven R. Bristow
IPC分类号： G01R31/319 , H03K5/135 , G06F9/00
CPC分类号： G01R31/31922 , H03K5/135
摘要： A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.
摘要翻译：提供了一种独特的定时系统，其允许用户编程具有来自固定频率时钟的可变周期和边缘的定时事件，并且具有大于固定参考频率的分辨率的分辨率。固有昂贵，不准确，需要重复校准的延迟元件被最小化。

5. 发明授权

US5606568A Method and apparatus for performing serial and parallel scan testing on an integrated circuit 失效
标题翻译：在集成电路上执行串行和并行扫描测试的方法和装置
公开(公告)号：US5606568A
公开(公告)日：1997-02-25
申请号：US565337
申请日：1995-11-30
申请人： Bruce D. Sudweeks
发明人： Bruce D. Sudweeks
IPC分类号： G01R31/319 , G06F11/00
CPC分类号： G01R31/31921 , G01R31/31908
摘要： An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.
摘要翻译：根据示例性实施例的集成电路测试装置包括被配置为存储处理器过程的第一存储器部分和被配置为同时存储并行集成电路测试向量和串行集成电路测试向量的第二存储器部分。处理器耦合到第一存储器部分和第二存储器部分。处理器被配置为执行处理器过程以同时操作并行集成电路测试向量和位于第二存储器中的串行集成电路测试向量来测试集成电路。本发明的优点包括同时存储串行和并行测试向量以及使用同时的串行和并行测试向量测试被测器件（DUT）的能力。串行和并行测试矢量的组合增加了测试设备的性能和效率。

6. 发明授权

US5521493A Semiconductor test system including a novel driver/load circuit 失效
标题翻译：半导体测试系统包括一个新颖的驱动器/负载电路
公开(公告)号：US5521493A
公开(公告)日：1996-05-28
申请号：US342697
申请日：1994-11-21
申请人： Thomas W. Persons
发明人： Thomas W. Persons
IPC分类号： G01R31/28 , G01R31/3167 , G01R31/319 , G01R31/22
CPC分类号： G01R31/3167 , G01R31/31924 , G01R31/2834
摘要： A novel pin electronics design and method is taught which serves to minimize the capacitive loading of the driver and load portion of the pin electronics. The driver and load circuitry are combined to form a novel driver/load circuit, thereby reducing capacitive loading, simplifying circuit structure, and improving the speed of operation of the test system and the accuracy of the test.
摘要翻译：教导了一种新颖的引脚电子设计和方法，其用于最小化引脚电子器件的驱动器和负载部分的电容负载。组合驱动器和负载电路以形成新颖的驱动器/负载电路，从而降低电容负载，简化电路结构，提高测试系统的运行速度和测试精度。

7. 发明授权

US4806852A Automatic test system with enhanced performance of timing generators 失效
标题翻译：自动测试系统具有增强的定时发生器性能
公开(公告)号：US4806852A
公开(公告)日：1989-02-21
申请号：US8030
申请日：1987-01-28
申请人： Richard Swan , Mike Catalano , Richard Feldman
发明人： Richard Swan , Mike Catalano , Richard Feldman
IPC分类号： G01R31/319 , G01R19/00 , G01R19/25
CPC分类号： G01R31/3191 , G01R31/31922
摘要： A unique automatic test system (100) is provided in which timing signals are generated in a novel manner as compared with prior art test systems. All adjustments for propagation delays of timing signals are made in a digital fashion, by adjusting the digital information which defines when an analog timing signal is to be generated. Deskewing of propagation delays is performed automatically under computer control, rather than by requiring careful adjustment of hardware deskewing elements. By adjusting for propagation skews digitally, propagation skews dependent on data values (logical 0 and logical 1) can be made. Furthermore, timing signals are provided by three timing edges, rather than by a timing pulse, thereby allowing more accurate generation of timing signals. The use of a complex switching matrix is eliminated by providing at least one timing generator per pin of the device under test, thereby eliminating complex hardware, propagation errors related to switching matrices, and providing enhanced capabilities for the user while simultaneously simplifying the problems associated with creating software used to control the test system during testing a device under test.
摘要翻译：提供了一种独特的自动测试系统（100），其中与现有技术的测试系统相比，以新颖的方式产生定时信号。通过调整定义模拟定时信号何时产生的数字信息，以数字方式进行定时信号的传播延迟的所有调整。在计算机控制下自动执行传播延迟的偏移，而不需要仔细调整硬件偏移元件。通过数字调整传播偏差，可以根据数据值（逻辑0和逻辑1）进行传播偏差。此外，定时信号由三个定时边缘而不是定时脉冲提供，从而允许更准确地产生定时信号。通过在被测器件的每个引脚提供至少一个定时发生器来消除复杂的开关矩阵的使用，从而消除复杂的硬件，与开关矩阵相关的传播错误，并为用户提供增强的功能，同时简化与在测试被测设备期间创建用于控制测试系统的软件。

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