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1. 发明授权

US11681799B2 Using trap cache segments to detect malicious processes 有权
公开(公告)号：US11681799B2
公开(公告)日：2023-06-20
申请号：US17132630
申请日：2020-12-23
申请人： International Business Machines Corporation
发明人： Brian A. Rinaldi , Clint A. Hardy , Lokesh M. Gupta , Kevin J. Ash
IPC分类号： G06F21/56 , G06F12/14
CPC分类号： G06F21/56 , G06F12/1458 , G06F2212/1052 , G06F2221/034
摘要： Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.

2. 发明授权

US09030377B2 Smart device notifications for surface computing 有权
标题翻译：用于表面计算的智能设备通知
公开(公告)号：US09030377B2
公开(公告)日：2015-05-12
申请号：US13954943
申请日：2013-07-30
申请人： International Business Machines Corporation
发明人： Denise A. Bell , Jana Jenkins , Jeffrey A. Kusnitz , Sarah Plantenberg
IPC分类号： G09G5/00 , H04M3/42 , H04M19/04 , G06F3/14
CPC分类号： H04M19/048 , G09G2356/00
摘要： Embodiments of the present invention provide a method and system for smart device notifications in surface computing. In an embodiment of the invention, a method for smart device notifications in surface computing includes registering in memory of a surface computing system, a placement of multiple different smart devices upon a surface of the surface computing system. The method also includes detecting a receipt of a notification in one of the smart devices. Finally, the method includes rendering in a visual display of the surface computing system, an indication of a particular one of the smart devices in which the receipt of the notification is detected.
摘要翻译：本发明的实施例提供了一种用于表面计算中智能设备通知的方法和系统。在本发明的实施例中，用于表面计算中的智能设备通知的方法包括在表面计算系统的存储器中注册多个不同智能设备在表面计算系统的表面上的放置。该方法还包括在智能设备之一中检测到通知的接收。最后，该方法包括在表面计算系统的视觉显示中呈现其中检测到通知的接收的智能设备中的特定一个的指示。

3. 发明授权

US08606984B2 Hierarchical to physical bus translation 失效
标题翻译：分层到物理总线翻译
公开(公告)号：US08606984B2
公开(公告)日：2013-12-10
申请号：US12758213
申请日：2010-04-12
申请人： William J. Armstrong , Scott N. Dunham , David R. Engebretsen , Gregory M. Nordstrom , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
发明人： William J. Armstrong , Scott N. Dunham , David R. Engebretsen , Gregory M. Nordstrom , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.
摘要翻译：在一个实施例中，分层总线编号与物理总线编号的转换和桥的桥标识符被写入到北芯片。接收到包含目的地的标识符的请求。确定标识符包括分层总线号码。响应于确定，目的地的标识符在请求中被替换为物理总线号和桥标识符。该请求被发送到由桥标识符标识的网桥。南芯片包括桥，南芯片通过点对点串行链路连接到北芯片。物理总线号标识将桥连接到设备的总线。请求包括请求向设备写入数据的配置写入请求。

4. 发明授权

US08169906B2 Controlling ATM traffic using bandwidth allocation technology 失效
标题翻译：使用带宽分配技术控制ATM流量
公开(公告)号：US08169906B2
公开(公告)日：2012-05-01
申请号：US11946057
申请日：2007-11-28
申请人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
发明人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28
CPC分类号： H04L47/32 , H04L12/5602 , H04L47/2408 , H04L47/2416 , H04L47/50 , H04L47/525 , H04L47/621 , H04L2012/5631 , H04L2012/5679
摘要： A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.
摘要翻译：公开了一种在计算机系统中管理异步传输模式（ATM）流量的方法和系统。计算机系统用于发送，接收或发送和接收多个ATM流。每个ATM流具有多个ATM信元，最小ATM带宽保证和最大ATM带宽。该方法和系统包括确定ATM流是否存在过量带宽。该方法和系统还包括在超额带宽周期期间适度地增加为每个ATM流发送的ATM信元的一部分。发送的ATM信元的部分不超过最大ATM带宽限制。如果ATM流提供足够的提供负载，则在流中发送的ATM信元的部分不小于最小ATM带宽保证。

5. 发明授权

US07609569B2 System and method for implementing row redundancy with reduced access time and reduced device area 有权
标题翻译：实现行冗余的系统和方法，减少了访问时间，减少了设备面积
公开(公告)号：US07609569B2
公开(公告)日：2009-10-27
申请号：US11941994
申请日：2007-11-19
申请人： Michael T. Fragano , Harold Pilo
发明人： Michael T. Fragano , Harold Pilo
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C29/844
摘要： A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry.
摘要翻译：用于在集成电路存储器件中实现行冗余的系统包括具有字线，位线和存储单元器件的一个或多个主子阵列，所述一个或多个主子阵列中的每一个包括与其相关联的一组支持电路。离散的冗余子阵列与主子阵列相关联，并且还包括与其相关联的一组支持电路。一个共同的全局位线由主子阵列和冗余子阵列共享，并且冗余转向控制电路与主子阵列和冗余子阵列相关联。冗余转向控制电路被配置为使得与冗余转向控制电路执行的地址比较操作并行执行主子阵列和冗余子阵列的字线激活。

6. 发明授权

US06977558B2 Self-adaptive voltage regulator for a phase-locked loop 失效
公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
IPC分类号： H03L7/08 , H03L7/14
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

7. 发明申请

US20030182595A1 Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) 失效
标题翻译：用于高速动态随机存取存储器（DRAM）的数据选通信号（DQS）
公开(公告)号：US20030182595A1
公开(公告)日：2003-09-25
申请号：US10102274
申请日：2002-03-20
申请人： International Busines Machines Corporation
发明人： Michael Joseph Carnevale , Paul Allen Ganfield , Daniel Frank Moertl
IPC分类号： H04B001/74
CPC分类号： G11C29/028 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50012 , G11C2207/2254
摘要： Embodiments are provided in which a method for delaying a strobe signal for a first pre-specified amount of time is described. A test signal is sent through a first number of delay books and a test is done as to whether it takes the test signal approximately a second pre-specified amount of time to pass the first number of delay books. Then, the number of delay books is increased or decreased by one at a time and until the number of delay books reaches a second number where it takes the test signal approximately the second pre-specified amount of time to pass the second number of delay books. From the second number, a third number of delay books is determined which is needed to cause a propagation delay approximately equal to the first pre-specified amount of time. Finally, the strobe signal is passed through the third number of delay books.
摘要翻译：提供了一种用于延迟第一预定时间量的选通信号的方法的实施例。通过第一数量的延迟书发送测试信号，并且测试是否将测试信号大约第二预定的时间量通过第一数量的延迟书。然后，延迟书的数量一次增加或减少，直到延迟书的数量达到第二个数字，其中测试信号大约第二个预定的时间量通过第二数量的延迟书。从第二个数字，确定第三数量的延迟书，其需要使传播延迟大致等于第一预先指定的时间量。最后，频闪信号通过第三数量的延迟书。

8. 发明授权

US11144251B2 Providing a global unique identifier for a storage volume 有权
公开(公告)号：US11144251B2
公开(公告)日：2021-10-12
申请号：US16163017
申请日：2018-10-17
申请人： INTERNATIONAL BUSINES MACHINES CORPORATION
发明人： Carlos D. Cavanna , Rafael Velez , Hamdi Roumani , Zixi Gu , Jeffrey Bloom
IPC分类号： G06F3/06 , H04L12/24 , G06F16/182
摘要： Provided are techniques for providing a global unique identifier for a storage volume. Under control of a storage initiator, a Global Universally Unique Identifier (GUUID) is identified for a storage volume of a storage device in a cloud system storing a plurality of storage devices, wherein the GUUID is generated for use with an ATA over Ethernet (AoE) protocol. The GUUID is stored in bytes of a packet header structure. Metadata is stored in remaining portions of the packet header structure. A request with the packet header structure is sent to a storage target.

9. 发明授权

US09772786B2 Address probing for transaction 有权
公开(公告)号：US09772786B2
公开(公告)日：2017-09-26
申请号：US14845359
申请日：2015-09-04
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Harold W. Cain, III , Dan F. Greiner , Michael K. Gschwind , Maged M. Michael , Eric M. Schwarz , Valentina Salapura , Timothy J. Slegel
IPC分类号： G06F12/00 , G06F3/06 , G06F9/46 , G06F12/0815 , G06F12/0844
CPC分类号： G06F3/0622 , G06F3/0659 , G06F3/0673 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0844 , G06F12/0862 , G06F12/1466 , G06F2212/6024 , G06F2212/621
摘要： Embodiments relate to address probing for a transaction. An aspect includes determining, before starting execution of a transaction, a plurality of addresses that will be used by the transaction during execution. Another aspect includes probing each address of the plurality of addresses to determine whether any of the plurality of addresses has an address conflict. Yet another aspect includes, based on determining that none of the plurality of addresses has an address conflict, starting execution of the transaction.

10. 发明授权

US09721092B2 Monitoring an application in a process virtual machine 有权
公开(公告)号：US09721092B2
公开(公告)日：2017-08-01
申请号：US14226930
申请日：2014-03-27
申请人： International Business Machines Corporation
发明人： Sean C. Foley
IPC分类号： G06F21/54 , G06F21/53 , G06F21/55
CPC分类号： G06F21/54 , G06F21/53 , G06F21/552
摘要： An application that runs in a process virtual machine is monitored by injecting listening code into a target class of the application. The listening code collects and forwards data to a monitoring agent. The target class is configured for monitoring according to alternative embodiments. In response to the process virtual machine providing notification of an event, such a loading the target class, the listening code may be injected into the target class. In another embodiment, the process virtual machine is configured to load a first mirror class containing a mirror entry point to the application. A mirror target class is loaded in response to a request to load the target class. The mirror target class contains a mirror entry point to the target class and the listening code. In another embodiment, listening code may be added to the target class before running the application.

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