专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09455203B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US09455203B2
公开(公告)日：2016-09-27
申请号：US14992739
申请日：2016-01-11
申请人： International Business Machines Corporation , Global Foundries Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/02 , H01L29/161 , H01L29/10
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。可以在高k电介质上形成伪栅极结构，并被蚀刻以在NMOS区域上形成开口，并且在PMOS区域上形成开口。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

2. 发明授权

US09449197B2 Pooling entropy to facilitate mobile device-based true random number generation 有权
标题翻译：汇集熵以促进基于移动设备的真实随机数生成
公开(公告)号：US09449197B2
公开(公告)日：2016-09-20
申请号：US13916655
申请日：2013-06-13
申请人： GLOBALFOUNDRIES Inc.
发明人： Matthew John Green , Leigh Stuart McLean , Peter Theodore Waltenberg
IPC分类号： G06F21/72 , G06F7/58
CPC分类号： G06F21/72 , G06F7/588 , G06F21/73
摘要： A mobile device operating system pools any available entropy. The resulting entropy pool is stored in device memory. When storing entropy in memory, preferably memory addresses are randomly allocated to prevent an attacker from capturing entropy that might have already been used to create a random number. The stored entropy pool provides a readily-available entropy source for any entropy required by the operating system or device applications. Then, when a cryptographic application requests a true random number, the operating system checks to determine whether the pool has available entropy and, if so, a portion of the entropy is provided to enable generation (e.g., by a TRNG) of a true random number that, in turn, may then be used for some cryptographic operation. After providing the entropy, the operating system clears the address locations that were used to provide it so that another entity cannot re-use the entropy.
摘要翻译：移动设备操作系统将任何可用的熵加载。所产生的熵池存储在设备存储器中。当在存储器中存储熵时，优选地随机分配存储器地址以防止攻击者捕获可能已经用于创建随机数的熵。存储的熵池为操作系统或设备应用所需的任何熵提供了一种易于获得的熵源。然后，当密码应用程序请求真正的随机数时，操作系统检查以确定池是否具有可用的熵，并且如果是，则提供熵的一部分以使得能够生成（例如通过TRNG）真实随机数然后可以将其用于一些加密操作。在提供熵后，操作系统清除用于提供它的地址位置，以便另一个实体不能重新使用熵。

3. 发明授权

US09426546B2 Maintaining a fabric name across a distributed switch 有权
标题翻译：在分布式交换机上维护一个Fabric名称
公开(公告)号：US09426546B2
公开(公告)日：2016-08-23
申请号：US14058545
申请日：2013-10-21
申请人： GLOBALFOUNDRIES INC.
发明人： Joachim Fenkes , Roger G. Hathorn , Sriharsha Jayanarayana , Henry J. May , Daniel Sentler , Sudheer R. Yelanduru
IPC分类号： H04Q11/00 , H04L12/24 , H04L29/12 , H04L12/721 , H04L12/28
CPC分类号： H04Q11/0067 , H04L41/0889 , H04L45/44 , H04L61/6004 , H04L61/6045 , H04Q11/0005 , H04Q2011/0088
摘要： Techniques are provided for distributing a fabric name to switching elements of a distributed switch configured to forward Fibre Channel over Ethernet (FCoE) frames. A distributed switch membership distributed (DMFD) message is transmitted that includes names of all switching elements in the distributed switch, and further includes a fabric descriptor that contains the fabric name.
摘要翻译：提供了一种技术，用于将结构名称分配给配置为转发以太网光纤通道（FCoE）帧的分布式交换机的交换元件。发送分布式交换机成员关系分发（DMFD）消息，其包括分布式交换机中的所有交换元件的名称，并且还包括包含结构名称的结构描述符。

4. 发明申请

US20160146879A1 METHODS, APPARATUS AND SYSTEM FOR VOLTAGE RAMP TESTING 有权
标题翻译：方法，电压测试仪器和系统
公开(公告)号：US20160146879A1
公开(公告)日：2016-05-26
申请号：US14553863
申请日：2014-11-25
申请人： GLOBAL FOUNDRIES INC. , International Business Machines Corporation
发明人： Suresh Uppal , Andreas Kerber , William McMahon , Eduard A. Cartier
IPC分类号： G01R31/14 , G01R31/28 , G01R31/26
CPC分类号： G01R31/14 , G01R31/2879
摘要： At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.
摘要翻译：本文公开的至少一种方法和系统涉及集成电路的测试。提供具有至少一个晶体管和至少一个电介质层的器件。在第一时间段期间提供第一电压以对器件进行压力测试。在第二时间期间提供第二电压，用于对作为第一电压的结果的电荷积累的至少一部分进行放电。第二电压具有与第一电压相反的极性。在第三时间段期间提供感测功能以确定压力测试的结果。获取，存储和/或发送与基于压力测试的结果的介电层击穿有关的数据。

5. 发明授权

US09041118B2 Replacement metal gate structure for CMOS device 有权
标题翻译： CMOS器件替代金属栅极结构
公开(公告)号：US09041118B2
公开(公告)日：2015-05-26
申请号：US14500914
申请日：2014-09-29
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70 , H01L27/092 , H01L29/49 , H01L29/423
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
摘要翻译：一种CMOS器件，其在nFET部分和pFET部分之间包括nFET部分，pFET部分和层间电介质。 nFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，直接物理接触的第二氮化钛层其中阻挡层和填充凹槽的其余部分的栅极金属。 pFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，阻挡层上的第二氮化钛层与第二氮化钛层直接物理接触的第三氮化钛层和填充凹槽的其余部分的栅极金属。

6. 发明申请

US20150091068A1 GATE ELECTRODE WITH A SHRINK SPACER 有权
标题翻译：带有收缩间隙的门电极
公开(公告)号：US20150091068A1
公开(公告)日：2015-04-02
申请号：US14043181
申请日：2013-10-01
申请人： GLOBAL FOUNDRIES Inc.
发明人： Tom Hasche , Sven Beyer , Gerhard Lembach , Alexander Ebermann
IPC分类号： H01L29/40 , H01L29/423
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/32139 , H01L21/823437 , H01L21/823468 , Y10S438/942 , Y10S438/947
摘要： A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.
摘要翻译：一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层，获得栅电极结构。一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。

7. 发明申请

US20140330786A1 COMPUTER-IMPLEMENTED METHODS AND SYSTEMS FOR REVISION CONTROL OF INTEGRATED CIRCUIT LAYOUT RECIPE FILES 审中-公开
标题翻译：计算机实现方法和系统用于集成电路布局文件的修改控制
公开(公告)号：US20140330786A1
公开(公告)日：2014-11-06
申请号：US13875942
申请日：2013-05-02
申请人： GLOBAL FOUNDRIES, INC.
发明人： Elizabeth John , Nanshu Chen
IPC分类号： G06F17/30
CPC分类号： G06F16/128
摘要： Computer-implemented methods and systems for providing revision control of integrated circuit device layout recipe files are provided. In an exemplary embodiment, a computer-implemented method for providing revision control of integrated circuit device layout recipe files includes storing recipe configuration files and recipe library files. Further, the method provides a user access to the recipe configuration files and recipe library files. The method includes creating with a computer a version snapshot of a selected recipe configuration file as revised by the user and of the other recipe configuration files and recipe library files as existing when the selected recipe configuration file is opened by the user. Further, the method includes providing the user access to all version snapshots for optical proximity correction (OPC) simulation.
摘要翻译：提供了用于提供集成电路设备配置文件的修订控制的计算机实现的方法和系统。在示例性实施例中，用于提供集成电路设备布局配方文件的修订控制的计算机实现的方法包括存储配方配置文件和配方库文件。此外，该方法提供用户对食谱配置文件和食谱库文件的访问。该方法包括：当用户打开所选择的食谱配置文件时，使用计算机创建由用户修改的所选食谱配置文件的版本快照和当前所选择的食谱配置文件所存在的其他食谱配置文件和食谱库文件。此外，该方法包括提供用户访问用于光学邻近校正（OPC）模拟的所有版本快照。

8. 发明申请

US20140264499A1 SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS 有权
标题翻译：具有接触电介质的半导体器件及相关制造方法
公开(公告)号：US20140264499A1
公开(公告)日：2014-09-18
申请号：US14288034
申请日：2014-05-27
申请人： GLOBAL FOUNDRIES Inc.
发明人： Lei Yuan , Jin Cho , Jongwook Kye
IPC分类号： H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76888 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L29/66477 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.
摘要翻译：提供半导体器件结构。示例性的半导体器件结构包括半导体材料的衬底和覆盖衬底的栅极结构。半导体衬底还包括形成在靠近栅极结构的衬底中的掺杂区域和覆盖掺杂区域的第一电介质材料。半导体衬底还包括形成在第一电介质材料中的导电触点，导电触点电连接到掺杂区域，以及覆盖在导电触点上的电介质盖。

9. 发明申请

US20140131809A1 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE 有权
标题翻译：替代CMOS器件的金属门结构
公开(公告)号：US20140131809A1
公开(公告)日：2014-05-15
申请号：US13676575
申请日：2012-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBAL FOUNDRIES INC
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/02 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal.
摘要翻译：一种制造用于CMOS器件的替代金属栅极结构的方法，包括在CMOS器件的nFET部分和pFET部分上形成伪栅极结构; 在所述虚拟栅极结构之间沉积层间电介质; 从nFET和pFET部分去除伪栅极结构，导致nFET部分上的凹槽和pFET部分上的凹陷; 将栅电介质共形沉积在nFET和pFET部分上的凹槽中; 将第一氮化钛，氮化钽和第二氮化钛的顺序层沉积到nFET和pFET部分上的凹槽中; 仅从nFET部分去除第二层氮化钛; 将第三层氮化钛沉积到nFET和pFET部分上的凹槽中; 并用金属填充nFET和pFET部分上的空腔的其余部分。

10. 发明授权

US08716094B1 FinFET formation using double patterning memorization 有权
标题翻译：使用双重图案记忆的FinFET形成
公开(公告)号：US08716094B1
公开(公告)日：2014-05-06
申请号：US13682769
申请日：2012-11-21
申请人： GLOBALFOUNDRIES Inc.
发明人： Chang Seo Park , Linus Jang , Jin Cho
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/311
CPC分类号： H01L29/66742 , H01L29/66795
摘要： Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.
摘要翻译：提供了使用双重图案记忆技术形成FinFET器件的方法。具体来说，首先将通过限定一组翅片，沉积多晶硅层和沉积硬掩模来形成器件。此后，将执行线的前端（FEOL）光刻蚀刻，光刻蚀刻（LELE）处理以在器件中形成一组沟槽。该组沟槽将填充随后抛光的氧化物层。此后，选择性地蚀刻器件以产生（例如，多晶硅）栅极图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式