专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150091068A1 GATE ELECTRODE WITH A SHRINK SPACER 有权
标题翻译：带有收缩间隙的门电极
公开(公告)号：US20150091068A1
公开(公告)日：2015-04-02
申请号：US14043181
申请日：2013-10-01
申请人： GLOBAL FOUNDRIES Inc.
发明人： Tom Hasche , Sven Beyer , Gerhard Lembach , Alexander Ebermann
IPC分类号： H01L29/40 , H01L29/423
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/32139 , H01L21/823437 , H01L21/823468 , Y10S438/942 , Y10S438/947
摘要： A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.
摘要翻译：一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层，获得栅电极结构。一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。

IPRDB

热门服务

关于我们

友情链接

联系方式