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1. 发明授权

US4754167A Programmable reference voltage generator for a read only memory 失效
标题翻译：可编程参考电压发生器，用于只读存储器
公开(公告)号：US4754167A
公开(公告)日：1988-06-28
申请号：US719928
申请日：1985-04-04
申请人： Cecil Conkle , Qazi A. S. M. Mahmood
发明人： Cecil Conkle , Qazi A. S. M. Mahmood
IPC分类号： G11C17/00 , G05F3/24 , G11C5/14 , G11C7/12 , G11C16/06 , G11C17/12 , H03K3/01 , G05F3/16
CPC分类号： G11C17/12 , G11C5/147 , G11C7/12
摘要： A read only memory (ROM) includes a series of bit lines biased by a reference voltage lead (102). The reference voltage lead (102) is connected to a first reference voltage generator (100) having an output impedance of 25 ohms and a second reference voltage generator (104) having an output impedance of 75,000 ohms. When the ROM is deselected, the first reference voltage generator (100) turns off and the bit lines are biased by the second reference voltage generator (100). However, when the ROM is selected, the first reference voltage generator (100) is turned on and biases the bit lines. In this way, a ROM is provided which can operate in a low power mode without decreasing the access time when the ROM goes from a deselected state into a selected state.
摘要翻译：只读存储器（ROM）包括由参考电压引线（102）偏置的一系列位线。参考电压引线（102）连接到具有25欧姆的输出阻抗的第一参考电压发生器（100）和具有75,000欧姆的输出阻抗的第二参考电压发生器（104）。当ROM被取消选择时，第一参考电压发生器（100）关闭，位线被第二参考电压发生器（100）偏置。然而，当选择ROM时，第一参考电压发生器（100）导通并偏置位线。以这种方式，提供可以在低功率模式下工作的ROM，而不会减小当ROM从取消选择状态进入选择状态时的访问时间。

2. 发明授权

US4409726A Method of making well regions for CMOS devices 失效
标题翻译：制造CMOS器件的良好区域的方法
公开(公告)号：US4409726A
公开(公告)日：1983-10-18
申请号：US366511
申请日：1982-04-08
申请人： Philip Shiota
发明人： Philip Shiota
IPC分类号： H01L21/033 , H01L21/266 , H01L21/762 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/76221 , H01L21/033 , H01L21/266 , H01L21/823892 , Y10S438/92
摘要： This invention significantly reduces the problem of undesired lateral diffusion of P type dopants into the P type active area. A thin oxide/nitride sandwich is formed on the surface of a semiconductor wafer and patterned to serve as a mask defining the to-be-formed active areas. An N type dopant implant is performed on the surface of the wafer to establish the desired field inversion threshold voltage. The wafer is then oxidized, with the oxide/nitride sandwich preventing oxide growth in the active areas. A layer of photoresist is applied to the wafer and patterned to expose the to-be-formed P well. That portion of the oxide exposed by the photoresist is removed, as is that portion of the substrate within the to-be-formed P well which contains N type dopants. P type impurities are then applied to the wafer. The photoresist is then removed and the P type dopants are diffused with little oxide growth to provide a P well having the desired dopant profile. Following this diffusion, a second, heavy concentration of P type dopant is implanted into the wafer at a sufficiently low energy to prevent the introduction of dopants into those portions of the wafer which are masked by the field oxide and the oxide/nitride sandwich areas. The oxide/nitride sandwich and the field oxide serve as masks, thus preventing the introduction of P type dopants in the field region or the active regions. Thus, the high concentration of P type dopants are introduced only in the periphery of the P well. The field oxide along the periphery of the P well is then regrown at a lower temperature than typically used for growing field oxide and diffusing dopants, thereby preventing substantial diffusion of the P type dopants. Thus, an active area within a P well is thereby formed wherein the width of the active area is not decreased due to P type dopant encroachment from the heavily doped periphery of the P well.
摘要翻译：本发明显着地减少了P型掺杂剂向P型有源区域的不期望的横向扩散的问题。在半导体晶片的表面上形成薄的氧化物/氮化物夹层，并将其图案化以作为限定要形成的有源区的掩模。在晶片的表面上执行N型掺杂剂注入以建立所需的场反转阈值电压。然后将晶片氧化，氧化物/氮化物夹层防止活性区域中的氧化物生长。将一层光致抗蚀剂施加到晶片并图案化以暴露待形成的P阱。去除由光致抗蚀剂曝光的氧化物的那部分，以及包含N型掺杂剂的待形成的P阱内的衬底的那部分。然后将P型杂质施加到晶片上。然后去除光致抗蚀剂，并且P型掺杂剂以少量氧化物生长扩散以提供具有所需掺杂剂分布的P阱。在该扩散之后，以足够低的能量将第二重量级的P型掺杂剂注入到晶片中，以防止将掺杂剂引入由场氧化物和氧化物/氮化物夹层区域掩蔽的晶片的那些部分。氧化物/氮化物夹层和场氧化物用作掩模，从而防止在场区域或活性区域中引入P型掺杂剂。因此，高浓度的P型掺杂剂仅在P阱的周围引入。然后沿着P阱周边的场氧化物在比通常用于生长场氧化物和扩散掺杂剂的较低温度下再生长，从而防止P型掺杂剂的实质扩散。因此，由此形成P阱内的有源区，其中由于P阱的重掺杂周边的P型掺杂剂侵入，有源区的宽度不降低。

3. 发明授权

US5838168A 3V/5V input buffer 失效
标题翻译： 3V / 5V输入缓冲器
公开(公告)号：US5838168A
公开(公告)日：1998-11-17
申请号：US708595
申请日：1996-09-05
申请人： Larry W. Petersen
发明人： Larry W. Petersen
IPC分类号： H03K19/0185 , H03K19/092
CPC分类号： H03K19/018521
摘要： An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit which is connected between an input and an output of the buffer circuit. When the first voltage is the intended operating voltage the at least one shortable transistor is shorted. The first operating voltage level meets the requirements of a CMOS device and the second operating voltage level meets the requirements of a TTL device. The shortable transistor can be either a p-channel or an n-channel transistor and the short can be done by a metal layer short, a polysilicon short, a depletion implant, or with vias during manufacture. Transistors in the buffer circuit are sized to provide an acceptable TTL device level trip point when the input buffer is operated at 5 volts and which also provides an acceptable CMOS device level trip point when the input buffer is operated at 3 volts. Transistors in the buffer circuit are provided to turn OFF the input buffer at the direction of an external circuit.
摘要翻译：能够在制造期间以可操作的电压电平在第一电源电压电平或第二电源电压电平下工作的输入缓冲器。至少一个可短路晶体管设置在电源电压输入端和连接在缓冲电路的输入端和输出端之间的缓冲电路之间。当第一电压是期望的工作电压时，至少一个可短路晶体管短路。第一个工作电压电平满足CMOS器件的要求，第二个工作电压电平满足TTL器件的要求。短路晶体管可以是p沟道或n沟道晶体管，并且短路可以通过金属层短，多晶硅短路，耗尽植入物或制造期间的通孔来实现。缓冲器电路中的晶体管的尺寸设定为当输入缓冲器在5伏特下操作时提供可接受的TTL器件电平跳变点，并且当输入缓冲器在3伏特下工作时也提供可接受的CMOS器件电平跳变点。提供缓冲电路中的晶体管，以在外部电路的方向上关闭输入缓冲器。

4. 发明授权

US4764691A CMOS programmable logic array using NOR gates for clocking 失效
标题翻译： CMOS可编程逻辑阵列使用NOR门进行时钟控制
公开(公告)号：US4764691A
公开(公告)日：1988-08-16
申请号：US787234
申请日：1985-10-15
申请人： Daniel R. Jochem
发明人： Daniel R. Jochem
IPC分类号： H01L21/82 , G06F15/78 , H03K19/00 , H03K19/096 , H03K19/173 , H03K19/177
CPC分类号： H03K19/0013 , H03K19/1772
摘要： A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock.
摘要翻译：一种可编程逻辑阵列100，其使用以紧凑布局布置的并行晶体管逻辑门150，用于快速信号传播。逻辑平面120或130之一可预充电，以便使用简单的单相时钟来显着降低功耗。

5. 发明授权

US4716586A State sequence dependent read only memory 失效
标题翻译：状态依赖的只读存储器
公开(公告)号：US4716586A
公开(公告)日：1987-12-29
申请号：US920935
申请日：1986-10-17
申请人： Jerry R. Bauer
发明人： Jerry R. Bauer
IPC分类号： G06F21/00 , G11C8/20 , H04L9/00
CPC分类号： G06F21/79 , G11C8/20
摘要： The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware. In all versions correct data will only be provided if the firmware is interrogated in the correct address sequence.
摘要翻译：持续监控被询问确定数据的坚定（ROM）地址。所选择的地址由地址检测装置识别。然后启动定时装置以对预设数量的地址访问，系统时钟周期或其他合适的定时装置进行计数。当定时器倒计时时，固件会提供替代地址。如果输入的地址是正确的序列，则替换的地址将与输入地址相同，并且ROM将提供正确的数据。否则，将提供不正确的数据。或者，在倒计时之后，输入地址可以与预期的传入地址进行比较。如果比较表示身份，那么输入地址可以提供给固件。否则，可以向固件的输入提供不正确的替代地址，或者可以在固件的输出上提供不正确的替代数据。在所有版本中，仅当固件以正确的地址顺序进行询问时才会提供正确的数据。

6. 发明授权

US4673933A Switch matrix encoding interface using common input/output parts 失效
标题翻译：使用公共输入/输出部分开关矩阵编码接口
公开(公告)号：US4673933A
公开(公告)日：1987-06-16
申请号：US551440
申请日：1983-11-14
申请人： Jerry R. Bauer
发明人： Jerry R. Bauer
IPC分类号： G06F3/023 , H03M11/20 , H04Q3/52 , H04Q1/00
CPC分类号： H03M11/20 , G06F3/023 , H04Q3/521
摘要： An encoding interface is provided between input data ports and strobe output ports of a (semiconductor integrated) circuit (chip) and an array of switches (40) is connected to a series of L input data lines and output lines (31-38), whereby the L lines can alternatively strobe the switch matrix to determine the (50) position of each switch. By having each line function either as an input line or an output line at a particular instant of time, the number of switches being served by a fixed number of total input and output lines is increased. For example, with eight total lines 28 switches are accommodated when the lines function either as input or output lines while when four separate lines are dedicated as input lines and four other lines dedicated as output lines only 16 switches are accommodated. In a further embodiment using two switches and a pair of oppositely disposed diodes at each cross point in the matrix the number of switches can be doubled (to 56 with eight dual input/output lines).
摘要翻译：在（半导体集成）电路（芯片）的输入数据端口和选通输出端口之间提供编码接口，并且开关阵列（40）连接到一系列L个输入数据线和输出线（31-38），由此L线可替代地选通开关矩阵以确定每个开关的（50）位置。通过使每条线路在特定时刻作为输入线路或输出线路，增加了由固定数量的总输入和输出线路服务的开关数量。例如，当线路用作输入或输出线路时，共有八条总线28个开关，而当四条独立线路专用为输入线路时，另外四条专用线作为输出线路只容纳16个开关。在另一实施例中，使用两个开关和在矩阵中的每个交叉点处的一对相对布置的二极管，开关的数量可以加倍（具有八个双输入/输出线）到56。

7. 发明授权

US4635002A Metal oxide semiconductor logarithmic voltage controlled oscillator 失效
标题翻译：金属氧化物半导体对数压控振荡器
公开(公告)号：US4635002A
公开(公告)日：1987-01-06
申请号：US638096
申请日：1984-08-06
申请人： G. Fred Riebeek
发明人： G. Fred Riebeek
IPC分类号： H03K4/06 , H03K7/06 , H03B5/14
CPC分类号： H03K4/06 , H03K7/06
摘要： Voltage controlled oscillator (50) provides an exponential transfer function. The frequency of the output signal of the voltage controlled oscillator varies exponentially with the input voltages (V.sub.IN1, V.sub.IN2) to the oscillator. The exponential transfer characteristic is provided by means of a MOS field effect transistor (19) biased in its subthreshold range.
摘要翻译：压控振荡器（50）提供指数传递函数。压控振荡器的输出信号的频率随振荡器的输入电压（VIN1，VIN2）呈指数关系而变化。指数传递特性由偏置在其阈值范围内的MOS场效应晶体管（19）提供。

8. 发明授权

US4590440A Phase locked loop with high and/or low frequency limit detectors for preventing false lock on harmonics 失效
标题翻译：具有高和/或低频限制检测器的锁相环，用于防止谐波错误锁定
公开(公告)号：US4590440A
公开(公告)日：1986-05-20
申请号：US628608
申请日：1984-07-06
申请人： Yusuf A. Haque , Ashraf K. Takla
发明人： Yusuf A. Haque , Ashraf K. Takla
IPC分类号： H03L7/08 , H03L7/06
CPC分类号： H03L7/08 , H03L2207/14 , Y10S331/02
摘要： A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop. If the output frequency of voltage controlled oscillator is below the predefined frequency range, the limiter circuit provides a high voltage output signal to the control input lead of the VCO in order to pull the input voltage of the voltage controlled oscillator to a voltage which corresponds with the proper operating frequency range of the phase locked loop.
摘要翻译：锁相环电路（16）包括消除谐波频率锁定的装置。锁相环包括压控振荡器（1），其提供通过相位检测器（4）与输入信号（Vin）进行比较的输出信号（Vout）。来自相位检测器的输出信号被积分，积分器（7）的输出信号置于压控振荡器的控制输入引线上。压控振荡器的输出信号被提供给频率检测器（14,17），其确定输出频率是否在预定范围内。如果输出频率高于预定范围，则限幅器电路（15）向VCO的控制输入引线提供低电压输出信号，以将VCO的输入电压拉至与适当工作范围相对应的电压的锁相环。如果压控振荡器的输出频率低于预定频率范围，则限幅器电路向VCO的控制输入引线提供高电压输出信号，以将压控振荡器的输入电压拉至与锁相环的正确工作频率范围。

9. 发明授权

US4541103A Digitally controlled syllabic filter for a delta modulator 失效
标题翻译：用于增量调制器的数字控制音节滤波器
公开(公告)号：US4541103A
公开(公告)日：1985-09-10
申请号：US468608
申请日：1983-02-22
申请人： Roubik Gregorian , Glenn Wegner
发明人： Roubik Gregorian , Glenn Wegner
IPC分类号： H03M3/02 , H03M3/04 , H04B12/04
CPC分类号： H03M3/024
摘要： A unique CVSD CODEC is provided utilizing switched capacitor technology. This CVSD CODEC includes a syllabic filter which provides one of a large number of possible step sizes, thereby allowing the CVSD CODEC to accurately track and convert a wide range of input voltages. The CVSD CODEC includes coincidence logic, which determines how accurately the input voltage is being tracked, and a syllabic filter which provides an appropriate step size based upon the output signals of the coincidence logic. Large step sizes are provided for converting input voltages having large magnitudes, and small step sizes are used to convert input voltages having small magnitudes, thereby providing the very accurate resolution of input voltages over the wide range of magnitudes, while minimizing the bit rate required.
摘要翻译：采用开关电容技术提供独特的CVSD CODEC。该CVSD CODEC包括提供大量可能步长之一的音节滤波器，从而允许CVSD CODEC准确地跟踪和转换宽范围的输入电压。 CVSD CODEC包括确定输入电压被跟踪的准确度的符合逻辑，以及基于重合逻辑的输出信号提供适当步长的音节滤波器。提供大步长用于转换具有大幅度的输入电压，并且使用小的步长来转换具有小幅度的输入电压，从而在宽幅度范围内提供非常精确的输入电压分辨率，同时最小化所需的比特率。

10. 发明授权

US4490629A High voltage circuits in low voltage CMOS process 失效
标题翻译：低电压CMOS工艺中的高压电路
公开(公告)号：US4490629A
公开(公告)日：1984-12-25
申请号：US376903
申请日：1982-05-10
申请人： Allen R. Barlow , Corey Petersen
发明人： Allen R. Barlow , Corey Petersen
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/118 , H03F3/42 , H03K19/0185 , H03K19/08 , H03K19/0944 , H03K19/0948 , H03K19/003 , H03K17/10 , H03K19/092 , H03K19/094
CPC分类号： H01L27/11898 , H03F3/42 , H03K19/018521 , H03K19/09448 , H03K19/0948
摘要： A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off.In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage.In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (C.sub.N), thus providing a first stage (101) which drives a second stage (100) having a plurality of P channel transistors and a plurality of N channel transistors (110, 111, 112), which provide the high voltage output voltage.In another embodiment of this invention, the first stage (101) is driven by a single ended control voltage (C.sub.N) and serves to drive a second stage (103) comprising a plurality of N channel transistors (110, 111, 112) and a plurality of bipolar transistors (120, 121), whereby said second stage provides the high voltage output signal.
摘要翻译：使用串联连接的多个N沟道晶体管（74,75,76）和多个P沟道晶体管（71,72,73）构造CMOS推挽输出缓冲器（171）。当P沟道晶体管截止时，施加到N沟道晶体管和P沟道晶体管的栅极的电压被选择为在P沟道晶体管中基本上均匀地划分高电压（+ V），并且基本上均匀地划分高电压跨越N沟道晶体管，当N沟道晶体管截止时。在本发明的另一个实施例中，形成N沟道和P沟道晶体管中的选定的晶体管以便具有高的漏极到体的击穿电压。在本发明的另一实施例中，多个N沟道和多个P沟道晶体管串联连接并由单端控制电压（CN）驱动，从而提供驱动第二级（100）的第一级（101））具有提供高电压输出电压的多个P沟道晶体管和多个N沟道晶体管（110,111,112）。在本发明的另一实施例中，第一级（101）由单端控制电压（CN）驱动，并用于驱动包括多个N沟道晶体管（110,111,112）的第二级（103）和多个双极晶体管（120,121），由此所述第二级提供高电压输出信号。

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