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1. 发明授权

US4590440A Phase locked loop with high and/or low frequency limit detectors for preventing false lock on harmonics 失效
标题翻译：具有高和/或低频限制检测器的锁相环，用于防止谐波错误锁定
公开(公告)号：US4590440A
公开(公告)日：1986-05-20
申请号：US628608
申请日：1984-07-06
申请人： Yusuf A. Haque , Ashraf K. Takla
发明人： Yusuf A. Haque , Ashraf K. Takla
IPC分类号： H03L7/08 , H03L7/06
CPC分类号： H03L7/08 , H03L2207/14 , Y10S331/02
摘要： A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop. If the output frequency of voltage controlled oscillator is below the predefined frequency range, the limiter circuit provides a high voltage output signal to the control input lead of the VCO in order to pull the input voltage of the voltage controlled oscillator to a voltage which corresponds with the proper operating frequency range of the phase locked loop.
摘要翻译：锁相环电路（16）包括消除谐波频率锁定的装置。锁相环包括压控振荡器（1），其提供通过相位检测器（4）与输入信号（Vin）进行比较的输出信号（Vout）。来自相位检测器的输出信号被积分，积分器（7）的输出信号置于压控振荡器的控制输入引线上。压控振荡器的输出信号被提供给频率检测器（14,17），其确定输出频率是否在预定范围内。如果输出频率高于预定范围，则限幅器电路（15）向VCO的控制输入引线提供低电压输出信号，以将VCO的输入电压拉至与适当工作范围相对应的电压的锁相环。如果压控振荡器的输出频率低于预定频率范围，则限幅器电路向VCO的控制输入引线提供高电压输出信号，以将压控振荡器的输入电压拉至与锁相环的正确工作频率范围。

2. 发明授权

US10289511B2 Differential physical layer device with testing capability 有权
公开(公告)号：US10289511B2
公开(公告)日：2019-05-14
申请号：US15241265
申请日：2016-08-19
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H04B3/46 , G06F11/22
摘要： A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

3. 发明授权

US6044123A Method and apparatus for fast clock recovery phase-locked loop with training capability 失效
标题翻译：具有训练能力的快速时钟恢复锁相环的方法和装置
公开(公告)号：US6044123A
公开(公告)日：2000-03-28
申请号：US733869
申请日：1996-10-17
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H03L7/113 , H03L7/10 , H03L7/14 , H03L7/18 , H04L7/00 , H04L7/033 , H04L7/10 , H03D3/24
CPC分类号： H03L7/10 , H03L7/143 , H03L7/18 , H04L7/0004 , H04L7/033 , H04L7/0331 , H04L7/10
摘要： A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.
摘要翻译：具有训练能力的锁相环，其以嵌入在数据信号中的已知频率的时钟信号的时钟恢复时间缩短。在数据信号可用之前，在训练模式下的锁相环采用本地振荡器信号获取频率和相位锁定。结果，PLL的输出基本上被锁定在嵌入预期数据信号中的时钟的频率上。为了实现该结果，在训练模式中，PLL将由第一分频器分频的本地振荡器信号与由第二分频器分频的输出时钟信号进行比较。那么PLL的输出时钟信号的频率等于本地振荡器的频率乘以第二分频器除数与第一分频器除数之比。当数据信号可用时，PLL在数据接收模式下工作。在这种模式下，PLL通常只需要获取锁相，因为已经在训练模式下获取了频率锁定。

4. 发明授权

US10664371B2 Differential physical layer device with testing capability 有权
公开(公告)号：US10664371B2
公开(公告)日：2020-05-26
申请号：US16372315
申请日：2019-04-01
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H04B1/40 , G06F11/22
摘要： A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

5. 发明申请

US20200097378A1 DIFFERENTIAL PHYSICAL LAYER DEVICE WITH TESTING CAPABILITY 审中-公开
公开(公告)号：US20200097378A1
公开(公告)日：2020-03-26
申请号：US16372315
申请日：2019-04-01
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： G06F11/22
摘要： A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

6. 发明申请

US20180052752A1 DIFFERENTIAL PHYSICAL LAYER DEVICE WITH TESTING CAPABILITY 审中-公开
公开(公告)号：US20180052752A1
公开(公告)日：2018-02-22
申请号：US15241265
申请日：2016-08-19
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： G06F11/22
CPC分类号： G06F11/2273 , G06F11/221
摘要： A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

7. 发明授权

US06295327B1 Method and apparatus for fast clock recovery phase-locked loop with training capability 失效
标题翻译：具有训练能力的快速时钟恢复锁相环的方法和装置
公开(公告)号：US06295327B1
公开(公告)日：2001-09-25
申请号：US09370606
申请日：1999-08-10
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H03D324
CPC分类号： H03L7/10 , H03L7/143 , H03L7/18 , H04L7/0004 , H04L7/033 , H04L7/0331 , H04L7/10
摘要： A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.
摘要翻译：具有训练能力的锁相环，其以嵌入在数据信号中的已知频率的时钟信号的时钟恢复时间缩短。在数据信号可用之前，在训练模式下的锁相环采用本地振荡器信号获取频率和相位锁定。结果，PLL的输出基本上被锁定在嵌入预期数据信号中的时钟的频率上。为了实现该结果，在训练模式中，PLL将由第一分频器分频的本地振荡器信号与由第二分频器分频的输出时钟信号进行比较。那么PLL的输出时钟信号的频率等于本地振荡器的频率乘以第二分频器除数与第一分频器除数之比。当数据信号可用时，PLL在数据接收模式下工作。在这种模式下，PLL通常只需要获取锁相，因为已经在训练模式下获取了频率锁定。

8. 发明授权

US5978425A Hybrid phase-locked loop employing analog and digital loop filters 失效
标题翻译：采用模拟和数字环路滤波器的混合锁相环
公开(公告)号：US5978425A
公开(公告)日：1999-11-02
申请号：US863039
申请日：1997-05-23
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H03H17/02 , H03L7/06 , H03L7/089 , H03L7/093 , H03D3/24
CPC分类号： H03L7/093 , H03L7/0891
摘要： The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.
摘要翻译：本发明提供一种混合锁相环（PLL），其分别包含用于数字和模拟调节的数字和模拟部分的输出信号。混合PLL设计简单。现有的受控振荡器（如电流控制振荡器（CCO））可与该混合PLL一起使用。混合PLL的数字和模拟部分与受控振荡器分离。数字部分用于对输出信号的频率进行第一次调整，例如在校准期间。模拟部分用于输出信号的精细相位和频率调整。

9. 发明授权

US5570054A Method and apparatus for adaptive clock deskewing 失效
标题翻译：自适应时钟校正的方法和装置
公开(公告)号：US5570054A
公开(公告)日：1996-10-29
申请号：US312355
申请日：1994-09-26
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： G06F1/10 , H03K5/00 , H03K5/15 , H03L7/07 , H03L7/081 , H03L7/089 , H03K5/13 , H03K3/01
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/1508 , H03L7/07 , H03L7/0812 , H03L7/0891
摘要： A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal. Each phase correction circuit includes a charge pump coupled to the output of the phase detector circuit, and a loop filter coupled to the output of the charge pump. The output of the loop filter is coupled to the input of the delay line. Each phase correction circuit is identically configured and the system clock signal is commonly provided to both the input of the phase detector in each phase correction circuit and a delay line clock reference input.
摘要翻译：系统时钟信号经由多个相位校正电路分配到多个负载装置，每个相位校正电路分别耦合到多对时钟信号导体的不同对。一对导体中的一个的近端耦合到延迟线的输出，并接收系统时钟信号的相位校正版本。该导体的远端在时钟连接节点处耦合到负载装置。时钟连接节点经由一对导体中的另一个反馈到相位校正电路。为了提供相等的传播延迟，第一和第二导体具有相等的路径长度。从负载装置节点反馈的时钟信号作为反馈输入耦合到三输入相位检测器电路。其他两个输入是从相位校正电路延迟线和系统时钟信号输出的时钟信号。每个相位校正电路包括耦合到相位检测器电路的输出的电荷泵和耦合到电荷泵的输出的环路滤波器。环路滤波器的输出耦合到延迟线的输入端。每个相位校正电路被相同配置，并且系统时钟信号通常提供给每个相位校正电路中的相位检测器的输入端和延迟线时钟基准输入端。

10. 发明授权

US5570053A Method and apparatus for averaging clock skewing in clock distribution network 失效
标题翻译：用于平均时钟分配网络中的时钟偏移的方法和装置
公开(公告)号：US5570053A
公开(公告)日：1996-10-29
申请号：US312026
申请日：1994-09-26
申请人： Ashraf K. Takla
发明人： Ashraf K. Takla
IPC分类号： H03K5/06 , G06F1/10 , H03K5/00 , H03K5/15 , H03K19/0175 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/089 , H03L7/00 , H03L7/18
CPC分类号： H03L7/0812 , G06F1/10 , H03K5/1506 , H03L7/07 , H03L7/087 , H03L7/0891
摘要： A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line. Each phase detector/charge pump combination generates a phase error correction signal corresponding to any delay associated with a given loop and device. The plurality of phase error correction signals are averaged in a loop filter and delay line, so that each phase corrected clock signal output from the delay line contains the average correction for all of the delays. In an alternate embodiment, the return loop is eliminated so that a single feedback signal representative of the delay induced by each load device is coupled to one input of a conventional two input phase detector. In this embodiment, the load effect on the distributed clock signals is averaged out.
摘要翻译：系统时钟信号通过公共环路滤波器和延迟线以及每个与不同负载相关联的多个相位检测器和电荷泵传送到多个负载装置。延迟线提供多个基本相同的相位校正时钟信号，每个时钟信号通过相关的导体部件耦合到相关的负载装置。在一个实施例中，每个导体构件包括由具有基本相同的路径长度的一对导体组成的环。出站导体近端的相位调整后的时钟信号作为第一反馈信号返回到相关相位检测器的一个输入端。另一个反馈信号包括沿着该对的第二导体从设备节点返回的时钟信号。相位检测器的第三输入是系统输入时钟信号，其也耦合到延迟线的参考输入。每个相位检测器/电荷泵组合产生对应于与给定回路和装置相关联的任何延迟的相位误差校正信号。多个相位误差校正信号在环路滤波器和延迟线中被平均，使得从延迟线输出的每个相位校正的时钟信号包含所有延迟的平均校正。在替代实施例中，消除了返回环，使得表示由每个负载装置引起的延迟的单个反馈信号耦合到常规两输入相位检测器的一个输入端。在本实施例中，对分布式时钟信号的负载影响被平均化。

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