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1. 发明授权

US6157587A Data sense arrangement for random access memory 失效
标题翻译：随机存取存储器的数据检测装置
公开(公告)号：US6157587A
公开(公告)日：2000-12-05
申请号：US965431
申请日：1997-11-06
申请人： Chitranjan N. Reddy , Vipul Patel
发明人： Chitranjan N. Reddy , Vipul Patel
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C7/065
摘要： A sensing circuit (30) for a random access memory (10) is disclosed. A CMOS sense amplifier (32) is coupled between bit line pairs which connected to I/O lines by a passgate (N4/N5). A pair of cross-coupled transistors (N6/N7) activated in synchronism with the passgate (N4/N5) is also disposed between the bit lines. The I/O line pairs each include a pair of cross coupled p-channel transistors (P4/P5). The combined action of the cross-coupled pairs (N6/N7) and (P4/P5) increase the sensing speed of the sensing circuit (30).
摘要翻译：公开了一种用于随机存取存储器（10）的感测电路（30）。 CMOS读出放大器（32）耦合在通过通孔（N4 / N5）连接到I / O线的位线对之间。与通路（N4 / N5）同步激活的一对交叉耦合晶体管（N6 / N7）也布置在位线之间。 I / O线对各自包括一对交叉耦合的p沟道晶体管（P4 / P5）。交叉耦合对（N6 / N7）和（P4 / P5）的组合作用增加了感测电路（30）的感测速度。

2. 发明授权

US6137746A High performance random access memory with multiple local I/O lines 有权
标题翻译：具有多个本地I / O线的高性能随机存取存储器
公开(公告)号：US6137746A
公开(公告)日：2000-10-24
申请号：US363083
申请日：1999-07-28
申请人： Subramani Kengeri , Chitranjan N. Reddy
发明人： Subramani Kengeri , Chitranjan N. Reddy
IPC分类号： G11C11/4097 , G11C8/00
CPC分类号： G11C11/4097
摘要： The present invention provides an apparatus and a method of reducing the time to drive the I/O lines by the sense amplifiers. In one embodiment of the present invention, local sense amplifier segments and associated local I/O lines are provided. The I/O lines are short in length and are connected to the sense amplifiers in the associated sense amplifier segments. The reduction in the length of the local I/O lines reduce the effective RC impedance of the I/O lines. Thus, the local sense amplifiers are smaller and drive the local I/O lines much faster. The present invention further provides global I/O lines connected to the local I/O lines. In a second embodiment of the present invention, the global I/O lines are driven by a second stage amplifier. In a third embodiment of the present invention, one global I/O line is provided for every local I/O line.
摘要翻译：本发明提供了一种减少由读出放大器驱动I / O线的时间的装置和方法。在本发明的一个实施例中，提供了本地读出放大器段和相关的本地I / O线。 I / O线的长度短，并连接到相关读出放大器段中的读出放大器。局部I / O线长度的减小降低了I / O线的有效RC阻抗。因此，局部感测放大器更小，驱动本地I / O线更快。本发明还提供了连接到本地I / O线的全局I / O线。在本发明的第二实施例中，全局I / O线由第二级放大器驱动。在本发明的第三实施例中，为每个本地I / O线提供一个全局I / O线。

3. 发明授权

US6133602A Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures 有权
公开(公告)号：US6133602A
公开(公告)日：2000-10-17
申请号：US448272
申请日：1999-11-24
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.

4. 发明授权

US6025214A Fusible link structure for semiconductor devices 失效
标题翻译：用于半导体器件的可熔连接结构
公开(公告)号：US6025214A
公开(公告)日：2000-02-15
申请号：US956192
申请日：1997-10-22
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).
摘要翻译：公开了一种用于半导体器件（200）的改进的激光熔丝连接结构及其制造方法（10）。图案化第一导电层以产生激光熔丝（202），然后用第一介电层（212）覆盖。在优选实施例中，蚀刻掩模层被沉积并图案化以在激光熔丝（202）的正上方形成熔丝蚀刻掩模（214）。保险丝蚀刻掩模（214）具有小于最小激光光斑尺寸的宽度，但足够大以保护激光熔丝（202）免受熔丝窗口过蚀刻，考虑到激光熔丝（202）之间的任何潜在的未对准）和熔丝蚀刻掩模（214）。

5. 发明授权

US6016270A Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations 失效
标题翻译：闪存架构利用时间共享地址总线方案和单独的存储单元访问路径，用于同时读/写操作
公开(公告)号：US6016270A
公开(公告)日：2000-01-18
申请号：US36558
申请日：1998-03-06
申请人： Damodar Reddy Thummalapally , Abhijit Ray
发明人： Damodar Reddy Thummalapally , Abhijit Ray
IPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/10 , G11C2216/22
摘要： A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is "free" for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.
摘要翻译：闪速存储器架构依赖于单个时间共享的地址总线，以使得当读操作针对当前未被标记用于算法操作的存储器单元块时，可以与算法操作同时执行读操作。在读取地址被锁存到为读操作选择的数组块之后，地址总线在读操作周期的其余部分是“空闲的”。在这个空闲时间期间，地址总线可用于算法操作，以将计数器地址加载到阵列中的活动标记块中。提供单独的全局数据I / O线以便于同时读取和算法操作。

6. 发明授权

US5892516A Perspective texture mapping circuit having pixel color interpolation mode and method thereof 失效
标题翻译：具有像素颜色插值模式的透视纹理映射电路及其方法
公开(公告)号：US5892516A
公开(公告)日：1999-04-06
申请号：US625479
申请日：1996-03-29
申请人： Thomas Alexander
发明人： Thomas Alexander
IPC分类号： G06T15/04 , G06T11/00
CPC分类号： G06T15/04
摘要： A perspective texture mapping circuit (10) is disclosed. In a perspective texture mapping mode, an inverse z gradient and corresponding inverse z polygon vertex value is loaded into a first interpolator circuit (14), and texture address product gradients with corresponding polygon vertex texture address product values are loaded into a second and third interpolator circuit (16 and 18). The first interpolator circuit (14) interpolates a sequence of inverse z values for the surface of the polygon. The second and third interpolator circuits (16 and 18) interpolate corresponding texture address product values for each interpolated inverse z value. The texture address product values are divided by the corresponding inverse z value in a divider circuit (12) to generate texture address values. Texture address values are coupled to texture memory (20) to generate texel values which are passed onto an output FIFO (26). In a color interpolation mode, each pixel includes three color component. Different color component gradients and vertex color component values are coupled to each interpolator circuit (14, 16 and 18) which interpolate corresponding color component values for the surface of the polygon. Corresponding color component values are coupled together to the output FIFO (26) to generate color pixels.
摘要翻译：公开了一种透视纹理映射电路（10）。在透视纹理映射模式中，将逆z渐变和相应的反z多边形顶点值加载到第一内插器电路（14）中，并将具有相应多边形顶点纹理地址乘积值的纹理地址乘积梯度加载到第二和第三内插器电路（16和18）。第一内插器电路（14）内插多边形表面的逆z值序列。第二和第三内插器电路（16和18）针对每个内插逆z值内插相应的纹理地址乘积值。纹理地址乘积值除以分频器电路（12）中相应的反z值，以产生纹理地址值。纹理地址值耦合到纹理存储器（20）以生成传递到输出FIFO（26）的纹素值。在颜色插值模式中，每个像素包括三个颜色分量。不同颜色分量梯度和顶点颜色分量值耦合到内插多边形表面的相应颜色分量值的每个内插器电路（14,16和18）。对应的颜色分量值耦合到输出FIFO（26）以产生彩色像素。

7. 发明授权

US5808959A Staggered pipeline access scheme for synchronous random access memory 失效
公开(公告)号：US5808959A
公开(公告)日：1998-09-15
申请号：US612044
申请日：1996-08-07
申请人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
发明人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1039
摘要： A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

8. 发明授权

US5767565A Semiconductor devices having cooperative mode option at assembly stage and method thereof 失效
标题翻译：在组装阶段具有协作模式选项的半导体器件及其方法
公开(公告)号：US5767565A
公开(公告)日：1998-06-16
申请号：US681206
申请日：1996-07-22
申请人： Chitranjan N. Reddy
发明人： Chitranjan N. Reddy
IPC分类号： G11C5/00 , G11C7/10 , H01L23/544
CPC分类号： G11C5/025 , G11C7/1006 , H01L24/06 , H01L27/0207 , H01L2224/04042 , H01L2224/48463 , H01L2224/49171 , H01L2924/14
摘要： Integrated circuits having single and multiple device modes are described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a "by n" input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a ".times.n" configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a ".times.2n" configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.
摘要翻译：描述具有单个和多个设备模式的集成电路。在优选的随机存取存储器（RAM）实施例中，与具有相同I / O配置的第二SRAM 10b相邻地制造具有“由n”输入/输出（I / O）配置的第一静态RAM（SRAM）10a。互连方案14跨越单独的设备划线18，其将SRAM 10a与SRAM 10b分离，并且在相邻的SRAM（10a和10b）之间传送地址，定时和控制信号。在需要具有“xn”配置的单个SRAM的情况下，沿着单个设备划线18切割晶片，从而切断互连方案14.在需要“x2n”配置的多个器件SRAM的情况下，锯切晶片进入多个器件管芯，并且互连方案保持不变。

9. 发明授权

US5670993A Display refresh system having reduced memory bandwidth 失效
标题翻译：显示具有减少内存带宽的刷新系统
公开(公告)号：US5670993A
公开(公告)日：1997-09-23
申请号：US486945
申请日：1995-06-07
申请人： Spencer H. Greene , Andrew D. Daniel
发明人： Spencer H. Greene , Andrew D. Daniel
IPC分类号： G09G5/39 , G09G5/395 , G09G5/36
CPC分类号： G09G5/395 , G09G5/39
摘要： A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).
摘要翻译：公开了一种显示刷新系统（10），其中显示图像作为具有连续可寻址单元的多个屏幕行（26）存储在屏幕存储器（12）中。冗余存储器（38）包括与每个屏幕行（26）对应的冗余行（48）。每个冗余行（48）存储指示屏幕行（26）内相同的连续可寻址单元的数量的游程长度数据。可寻址单元以相应的运行长度写入FIFO（54）。寄存器中继器（56）在FIFO输出（62）处重复等于运行长度的次数的可寻址单元。游程长度用于将刷新地址提升到屏幕行（26）内的下一组相同的连续可寻址单元。

10. 发明授权

US5638090A Window-dependent brightness/tint control for video digital-to-analog converters 失效
标题翻译：视频数/模转换器的窗口相关亮度/色调控制
公开(公告)号：US5638090A
公开(公告)日：1997-06-10
申请号：US347720
申请日：1994-12-01
申请人： William N. Schnaitter , Spencer H. Greene , Andrew Daniel
发明人： William N. Schnaitter , Spencer H. Greene , Andrew Daniel
IPC分类号： G09G1/28 , G09G5/14 , H04N5/57 , H04N9/64 , G09G5/04
CPC分类号： G09G1/285 , G09G5/14 , H04N9/643 , G09G2320/0606 , G09G2320/0626 , G09G2320/0666 , G09G2320/0686 , G09G2340/125 , H04N5/57
摘要： A display control circuit controls the outputs of the three video DACs of an RGB monitor on a window-to-window basis to enable the display of motion video and text on the same screen with different brightness and/or tint. A digital overdrive signal, synchronized to the video DAC digital inputs, is used to enable added DAC elements for the pixels in the video windows only. Stored digital instructions determine how many and which added DAC elements are enabled by the overdrive bit(s). By storing different instructions for each of the three video DACs, the circuit may also provide window-dependent tint control. By increasing the number of bits of digital data synchronized to the digital DAC inputs, the stored instructions may be reduced or eliminated. In this case, each of several windows may be set to differing brightness and tint levels. As many different values of brightness and tint may be available as desired by increasing the number of synchronized input enabling bits and the number and strength of the added DAC elements.
摘要翻译：显示控制电路在窗口对窗口的基础上控制RGB监视器的三个视频DAC的输出，以使得能够以不同的亮度和/或色调在同一屏幕上显示运动视频和文本。与视频DAC数字输入同步的数字超速信号用于仅为视频窗口中的像素启用添加的DAC元件。存储的数字指令确定多少，哪些添加的DAC元件由过载驱动位使能。通过为三个视频DAC中的每一个存储不同的指令，电路还可以提供依赖于窗口的色调控制。通过增加与数字DAC输入同步的数字数据的位数，可以减少或消除存储的指令。在这种情况下，可以将多个窗口中的每一个设置为不同的亮度和色调级别。通过增加同步输入使能位的数目和增加的DAC元件的数量和强度，可以根据需要提供许多不同的亮度和色调值。

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