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1. 发明授权

US5808959A Staggered pipeline access scheme for synchronous random access memory 失效
公开(公告)号：US5808959A
公开(公告)日：1998-09-15
申请号：US612044
申请日：1996-08-07
申请人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
发明人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1039
摘要： A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

2. 发明授权

US5872742A Staggered pipeline access scheme for synchronous random access memory 失效
标题翻译：用于同步随机存取存储器的交错管道访问方案
公开(公告)号：US5872742A
公开(公告)日：1999-02-16
申请号：US63529
申请日：1998-04-21
申请人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
发明人： Subramani Kengeri , Darryl G. Walker , Kenneth A. Poteet , Chitranjan N. Reddy
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1039
摘要： A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).
摘要翻译：公开了与外部时钟同步工作的静态随机存取存储器（SRAM）（10）。同步SRAM（10）包括用于在外部时钟的上升沿之前的建立时间内解码外部地址的透明地址电路（14）。定时和控制电路（18）与外部时钟的上升沿同步地产生字线使能（WLE）信号。激活时，WLE激活字线驱动器（34），当不活动时，WLE均衡位线。 WLE被施加到第一延迟电路（60）以产生感测信号（SA）。 SA激活感测电路（46）并使WLE信号无效。实现连续流水线访问，使得当地址被解码时，位线是均衡的，并且来自先前地址的数据通过数据I / O路径传播（16）。

3. 发明授权

US10365318B2 Testing and setting performance parameters in a semiconductor device and method therefor 有权
公开(公告)号：US10365318B2
公开(公告)日：2019-07-30
申请号：US16017217
申请日：2018-06-25
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01R31/02 , G11C7/04 , G01R31/26 , G01R31/28 , G11C29/02 , G11C29/50 , G11C11/406 , G11C29/00
摘要： A method of providing a temperature value from a dynamic random access memory (DRAM) device can include receiving a test mode command that activates a temperature value output mode of operation; providing the temperature value to an output buffer circuit; providing an enable signal to the output buffer circuit; and outputting the temperature value that indicates a temperature range, the temperature value is outputted from the output buffer circuit to at least one terminal that is electrically connected external to the DRAM device; wherein the temperature value includes at least 5 binary bits.

4. 发明授权

US10262976B1 Package including a plurality of stacked semiconductor devices, an interposer and interface connections 有权
公开(公告)号：US10262976B1
公开(公告)日：2019-04-16
申请号：US16238760
申请日：2019-01-03
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G11C16/04 , H01L25/065 , G11C11/4099 , G11C5/14 , G11C11/4093 , H01L23/00 , H01L49/02 , H01L23/48 , G11C5/02 , G11C11/4074 , G11C11/4094 , H01L21/768 , G11C5/10 , G11C11/408 , G11C11/4063 , H01L27/108
摘要： A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. A first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate, separated from one another by at least one capacitor dielectric. A first capacitor node can be electrically connected to the first terminal of the first capacitor. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The at least one essentially vertically formed conductive portion can comprise polysilicon.

5. 发明授权

US10260962B2 Semiconductor device having temperature sensor circuit that detects a temperature range upper limit value and a temperature range lower limit value 有权
公开(公告)号：US10260962B2
公开(公告)日：2019-04-16
申请号：US15948919
申请日：2018-04-09
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01K7/16 , G11C7/00 , G01K7/00 , G01K13/00 , H03K3/012 , H03K17/14 , H03K17/687 , G11C7/04 , G11C11/406 , H03K17/22 , H03K21/10 , G11C11/4074 , G11C11/4093 , G11C11/4096 , G11C11/407 , G01K7/01 , G01K3/00
摘要： A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.

6. 发明申请

US20190074055A1 SEMICONDUCTOR DEVICES, CIRCUITS AND METHODS FOR READ AND/OR WRITE ASSIST OF AN SRAM CIRCUIT PORTION BASED ON VOLTAGE DETECTION AND/OR TEMPERATURE DETECTION CIRCUITS 审中-公开
公开(公告)号：US20190074055A1
公开(公告)日：2019-03-07
申请号：US16172787
申请日：2018-10-27
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G11C11/419 , G11C11/412 , G11C7/04 , G11C5/14 , G11C29/02 , G11C7/22
摘要： A method of operating a semiconductor device powered by a first power supply potential can include generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read or write assist signal having a read or write assist enable logic level in response to the first latched voltage signal; and altering a read or write operation to a static random access memory (SRAM) cell in response to the at least one read or write assist signal having the read or write assist enable logic level as compared to when the at least one read or write assist signal has a read or write assist disable logic level.

7. 发明申请

US20180231421A1 SEMICONDUCTOR DEVICE HAVING TEMPERATURE SENSOR CIRCUIT THAT DETECTS A TEMPERATURE RANGE UPPER LIMIT VALUE AND A TEMPERATURE RANGE LOWER LIMIT VALUE 审中-公开
公开(公告)号：US20180231421A1
公开(公告)日：2018-08-16
申请号：US15948919
申请日：2018-04-09
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01K7/16 , G01K7/00 , G01K7/01 , G01K13/00 , G11C7/00 , G11C7/04 , G11C11/407 , G11C11/4074 , G11C11/4093 , G11C11/4096 , G11C11/406 , H03K3/012 , H03K17/14 , H03K17/22 , H03K17/687 , H03K21/10 , G01K3/00
CPC分类号： G01K7/16 , G01K3/005 , G01K7/00 , G01K7/01 , G01K13/00 , G11C7/00 , G11C7/04 , G11C11/40626 , G11C11/407 , G11C11/4074 , G11C11/4093 , G11C11/4096 , H03K3/012 , H03K17/145 , H03K17/223 , H03K17/687 , H03K21/10 , Y10T307/773
摘要： A device that operates over a plurality of predetermined temperature ranges that can include a subthreshold operating circuit including a first insulated gate field effect device (IGFET) having a first conductivity type. The first IGFET can be coupled to receive a first back body bias potential that changes according to the temperature range in which the device is operating. The subthreshold operating circuit can operate at a power supply potential below a threshold voltage of the first IGFET.

8. 发明授权

US10006959B2 Testing and setting performance parameters in a semiconductor device and method therefor 有权
公开(公告)号：US10006959B2
公开(公告)日：2018-06-26
申请号：US14484546
申请日：2014-09-12
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01R31/26 , G01R31/02 , G11C7/04 , G11C29/02 , G11C29/50 , G01R31/28 , G11C29/00 , G11C11/406
CPC分类号： G01R31/2628 , G01R31/025 , G01R31/2856 , G01R31/2875 , G11C7/04 , G11C11/40615 , G11C11/40626 , G11C29/006 , G11C29/023 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5002
摘要： A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

9. 发明授权

US09997513B1 Package including a plurality of stacked semiconductor devices having area efficient ESD protection 有权
公开(公告)号：US09997513B1
公开(公告)日：2018-06-12
申请号：US15645196
申请日：2017-07-10
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： H01L29/49 , H01L27/02 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/60 , H01L25/18 , H01L2225/06527 , H01L2225/06544 , H01L2225/06565
摘要： A multi-chip device can include stacked semiconductor devices including a top and bottom semiconductor device. The top semiconductor device can include a first circuit. The bottom semiconductor device can include a first through via and a first ESD protection circuit electrically connected to an external electrical connection of the device. The first ESD protection circuit can include a first ESD protection structure. The first through via can provide an electrical connection through the bottom semiconductor device between the external electrical connection and a first terminal of the first circuit, which can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure.

10. 发明授权

US09939330B2 Semiconductor device having subthreshold operating circuits including a back body bias potential based on temperature range 有权
公开(公告)号：US09939330B2
公开(公告)日：2018-04-10
申请号：US14265668
申请日：2014-04-30
申请人： Darryl G. Walker
发明人： Darryl G. Walker
IPC分类号： G01K7/16 , G11C7/00 , G01K7/00 , G01K13/00 , H03K3/012 , H03K17/14 , H03K17/687 , G11C7/04 , G11C11/406 , H03K17/22 , H03K21/10 , G11C11/4074 , G11C11/4093 , G11C11/4096 , G11C11/407 , G01K7/01 , G01K3/00
CPC分类号： G01K7/16 , G01K3/005 , G01K7/00 , G01K7/01 , G01K13/00 , G11C7/00 , G11C7/04 , G11C11/40626 , G11C11/407 , G11C11/4074 , G11C11/4093 , G11C11/4096 , H03K3/012 , H03K17/145 , H03K17/223 , H03K17/687 , H03K21/10 , Y10T307/773
摘要： A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

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