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1. 发明申请

US20130198703A1 Virtual Flat Traversal Of A Hierarchical Circuit Design 审中-公开
标题翻译：分层电路设计的虚拟平面遍历
公开(公告)号：US20130198703A1
公开(公告)日：2013-08-01
申请号：US13592304
申请日：2012-08-22
申请人： Ziyang Lu , Fedor G. Pikus , Phillip A. Brooks
发明人： Ziyang Lu , Fedor G. Pikus , Phillip A. Brooks
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.
摘要翻译：配置模板反映了分层电路设计数据中描述的配置信息。对象配置信息将包括模板通用配置信息和实例特定配置信息。模板通用配置信息是分层电路设计数据中对应单元的所有实例的公共配置信息。然后，实例特定配置信息是分层电路设计数据中相应小区的一个或多个特定实例的特定配置信息。在生成对象配置模板之后，配置信息分析单元使用包含在对象配置模板中的对象配置信息来识别具有与定义的配置准则相匹配的配置数据的对象。

2. 发明申请

US20130080985A1 ELECTROSTATIC DAMAGE PROTECTION CIRCUITRY VERIFICATION 审中-公开
标题翻译：静电损伤保护电路验证
公开(公告)号：US20130080985A1
公开(公告)日：2013-03-28
申请号：US13426595
申请日：2012-03-21
申请人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
发明人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
摘要翻译：用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。基于互连线的特性和指定的最大阻抗分量值创建分析窗口。窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。

3. 发明申请

US20100185995A1 Electrostatic Damage Protection Circuitry Verification 审中-公开
标题翻译：静电损伤保护电路验证
公开(公告)号：US20100185995A1
公开(公告)日：2010-07-22
申请号：US12541906
申请日：2009-08-14
申请人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
发明人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
摘要翻译：用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。基于互连线的特性和指定的最大阻抗分量值创建分析窗口。窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。

4. 发明申请

US20120054703A1 Virtual Flat Traversal Of A Hierarchical Circuit Design 审中-公开
标题翻译：分层电路设计的虚拟平面遍历
公开(公告)号：US20120054703A1
公开(公告)日：2012-03-01
申请号：US12868717
申请日：2010-08-25
申请人： G. Fedor Pikus , Ziyang Lu , Phillip A. Brooks
发明人： G. Fedor Pikus , Ziyang Lu , Phillip A. Brooks
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.
摘要翻译：配置模板反映了分层电路设计数据中描述的配置信息。对象配置信息将包括模板通用配置信息和实例特定配置信息。模板通用配置信息是分层电路设计数据中对应单元的所有实例的公共配置信息。然后，实例特定配置信息是分层电路设计数据中相应小区的一个或多个特定实例的特定配置信息。在生成对象配置模板之后，配置信息分析单元使用包含在对象配置模板中的对象配置信息来识别具有与定义的配置准则相匹配的配置数据的对象。

5. 发明授权

US06879927B1 Communication interface for virtual IC tester 失效
标题翻译：虚拟IC测试仪的通讯接口
公开(公告)号：US06879927B1
公开(公告)日：2005-04-12
申请号：US10624614
申请日：2003-07-21
申请人： Ziyang Lu
发明人： Ziyang Lu
IPC分类号： G06F19/00
CPC分类号： G01R31/318357 , G01R31/31917
摘要： A method of verifying test data for testing an integrated circuit device having multiple device time domains includes selecting a virtual tester time domain and, if the cycle duration of the virtual tester time domain is equal to the cycle duration of one of the multiple device time domains, translating the test data for each device time domain other than that one time domain to the virtual tester time domain and otherwise translating the test data for each device time domain to the virtual tester time domain. The translated test data is then applied to a device logic simulator that simulates integrated circuit device.
摘要翻译：验证用于测试具有多个设备时间域的集成电路设备的测试数据的方法包括选择虚拟测试仪时域，并且如果虚拟测试仪时域的周期持续时间等于多个设备时域之一的周期持续时间将除该一个时域之外的每个设备时域的测试数据转换到虚拟测试仪时域，然后将每个设备时域的测试数据转换为虚拟测试仪时域。然后将翻译的测试数据应用于模拟集成电路器件的器件逻辑仿真器。

6. 发明申请

US20100306720A1 Programmable Electrical Rule Checking 审中-公开
标题翻译：可编程电气规则检查
公开(公告)号：US20100306720A1
公开(公告)日：2010-12-02
申请号：US12474240
申请日：2009-05-28
申请人： F. G. Pikus , Ziyang Lu , Philip Brooks
发明人： F. G. Pikus , Ziyang Lu , Philip Brooks
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Electrical rule checking techniques for analyzing integrated circuit design data to identify specified circuit element configurations. Both tools and methods implementing these techniques may be employed to identify circuit element configurations using both logical and physical layout information for the design data. A set of commands are provided that will allow a user to program a programmable electrical rule check tool to identify a wide variety of circuit element configurations, using both logical and physical layout data, as desired by the user.
摘要翻译：用于分析集成电路设计数据以识别指定的电路元件配置的电气规则检查技术。可以采用实现这些技术的两种工具和方法来识别用于设计数据的逻辑和物理布局信息的电路元件配置。提供了一组命令，其允许用户编程可编程电气规则检查工具，以根据用户的需要使用逻辑和物理布局数据两者来识别各种各样的电路元件配置。

7. 发明申请

US20060236327A1 GUI-based API for test systems 审中-公开
标题翻译：基于GUI的测试系统API
公开(公告)号：US20060236327A1
公开(公告)日：2006-10-19
申请号：US11108018
申请日：2005-04-14
申请人： Ziyang Lu
发明人： Ziyang Lu
IPC分类号： G06F9/44 , G06F3/00
CPC分类号： G06F11/3664
摘要： A GUI-based API for a test system provides a user-friendly interface for generating API function calls in one of several different programming languages, as selected by the user. The GUI-based API prompts the user to select from a list of valid API functions, which are generated based on the test system configuration. The values for the selected API function parameters are then specified by selecting from a valid list of choices or by entering an arbitrary value. The valid list of choices presented to the user for selection is generated based on the test system configuration and on the prior parameter values specified by the user. For API functions including parameters that have a main parameter and optional parameters, input interfaces for specifying the values for the optional parameters are also presented to the user. Every parameter of the selected API function is processed, so that when the last parameter is processed, an appropriate end of function signature is automatically inserted.
摘要翻译：用于测试系统的基于GUI的API提供用户友好的界面，用于根据用户选择的几种不同的编程语言之一生成API函数调用。基于GUI的API提示用户从基于测试系统配置生成的有效API函数列表中进行选择。然后通过从有效的选择列表中选择或输入任意值来指定所选API函数参数的值。基于测试系统配置和用户指定的先前参数值，生成提供给用户进行选择的有效选择列表。对于包括具有主参数和可选参数的参数的API函数，还可以向用户呈现用于指定可选参数值的输入接口。处理所选API函数的每个参数，以便当处理最后一个参数时，将自动插入适当的功能签名结束。

8. 发明申请

US20070294580A1 VIRTUAL TESTER ARCHITECTURE 审中-公开
标题翻译：虚拟测试架构
公开(公告)号：US20070294580A1
公开(公告)日：2007-12-20
申请号：US11421332
申请日：2006-05-31
申请人： Ziyang Lu
发明人： Ziyang Lu
IPC分类号： G06F11/00
CPC分类号： G01R31/318357
摘要： A virtual tester, for testing a device logic simulator, includes multiple virtual instruments that generate stimulus messages for delivery to the device logic simulator and for receiving response messages generated by the device logic simulator. Each virtual instrument models a corresponding hardware test instrument and comprises a concrete instrument model that behaves in a manner corresponding to the corresponding hardware test instrument and also comprises an abstract interface that is independent of the behavior of the corresponding hardware test instrument. At least one virtual instrument generates sync messages for coordinating operation of the virtual instruments. A virtual tester engine receives the sync messages and executes an algorithm in which the virtual tester engine cyclically identifies sync messages that pertain to a current operating cycle, communicates sync messages to each virtual instrument, validates sync messages based on responses by the virtual instruments to the sync messages and communicates the validated sync messages to each virtual instrument. A virtual instrument that is specified by a validated sync message performs a test activity based on the validated sync message and a user test program.
摘要翻译：用于测试设备逻辑模拟器的虚拟测试器包括产生用于传送到设备逻辑模拟器的刺激消息并且用于接收由设备逻辑模拟器产生的响应消息的多个虚拟仪器。每个虚拟仪器对相应的硬件测试仪器进行建模，并且包括以对应于相应的硬件测试仪器的方式行为的具体仪器模型，并且还包括独立于相应的硬件测试仪器的行为的抽象接口。至少一个虚拟仪器产生用于协调虚拟仪器的操作的同步消息。虚拟测试仪引擎接收同步消息并执行一种算法，其中虚拟测试仪引擎周期性地识别与当前操作周期相关的同步消息，将同步消息传送到每个虚拟仪器，根据虚拟仪器对虚拟仪器的响应来验证同步消息同步消息并将验证的同步消息传送到每个虚拟仪器。由验证的同步消息指定的虚拟仪器根据验证的同步消息和用户测试程序执行测试活动。

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