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1. 发明授权

US08751981B2 Logic injection 有权
标题翻译：逻辑注入
公开(公告)号：US08751981B2
公开(公告)日：2014-06-10
申请号：US13532484
申请日：2012-06-25
申请人： Fedor G. Pikus , Kobi Kresh
发明人： Fedor G. Pikus , Kobi Kresh
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F17/5081
摘要： A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.
摘要翻译：一种减少电路列表的技术。根据该技术的示例，分析电路列表的至少一部分以识别由多个电路部件组成的电路结构的出现。对于定义的电路结构的每个识别的出现，对应于多个分量创建注入数据对象，并且将注入数据对象替换为电路列表的部分来代替多个分量。对于定义结构的每次出现，可以由相应的注入数据对象确定并包含所定义结构的出现的一个或多个属性。

2. 发明授权

US07222312B2 Secure exchange of information in electronic design automation 有权
标题翻译：在电子设计自动化中安全交换信息
公开(公告)号：US07222312B2
公开(公告)日：2007-05-22
申请号：US10895485
申请日：2004-07-20
申请人： John G. Ferguson , Fedor G. Pikus , Kyohei Sakajiri , Laurence W. Grodd
发明人： John G. Ferguson , Fedor G. Pikus , Kyohei Sakajiri , Laurence W. Grodd
IPC分类号： G06F17/50 , G04Q99/00 , H04L9/00 , H04L9/3213
CPC分类号： G06Q40/04 , H04L9/0838 , H04L2209/16
摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.
摘要翻译：这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。可能会生成错误报告，而不会泄露安全规则。

3. 发明授权

US09507902B2 Simultaneous multi-layer fill generation 有权
公开(公告)号：US09507902B2
公开(公告)日：2016-11-29
申请号：US13093828
申请日：2011-04-25
申请人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
发明人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
IPC分类号： G06F17/50 , G03F1/44 , H01L27/02
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.

4. 发明授权

US08612919B2 Model-based design verification 有权
标题翻译：基于模型的设计验证
公开(公告)号：US08612919B2
公开(公告)日：2013-12-17
申请号：US11986564
申请日：2007-11-20
申请人： Fedor G. Pikus , David A. Abercrombie
发明人： Fedor G. Pikus , David A. Abercrombie
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5081
摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.
摘要翻译：模拟设计规则检查工具分析微设计设计，例如集成电路设计，以识别共享指定关系的几何元素的出现。当工具识别这些几何元素的这种出现时，它将将这些几何元素相关联或“聚集”到一个可识别的单元中。对于几何元素的特定“簇”，模拟设计规则检查工具将确定用户所需的测量值或测量值。一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的功能。

5. 发明申请

US20130198703A1 Virtual Flat Traversal Of A Hierarchical Circuit Design 审中-公开
标题翻译：分层电路设计的虚拟平面遍历
公开(公告)号：US20130198703A1
公开(公告)日：2013-08-01
申请号：US13592304
申请日：2012-08-22
申请人： Ziyang Lu , Fedor G. Pikus , Phillip A. Brooks
发明人： Ziyang Lu , Fedor G. Pikus , Phillip A. Brooks
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design data. The instance specific configuration information is then configuration information that is particular to one or more specific instantiations of the corresponding cell in the hierarchical circuit design data. After the object configuration templates have been generated, a configuration information analysis unit uses the object configuration information contained in the object configuration templates to identify objects having configuration data that match defined configuration criteria.
摘要翻译：配置模板反映了分层电路设计数据中描述的配置信息。对象配置信息将包括模板通用配置信息和实例特定配置信息。模板通用配置信息是分层电路设计数据中对应单元的所有实例的公共配置信息。然后，实例特定配置信息是分层电路设计数据中相应小区的一个或多个特定实例的特定配置信息。在生成对象配置模板之后，配置信息分析单元使用包含在对象配置模板中的对象配置信息来识别具有与定义的配置准则相匹配的配置数据的对象。

6. 发明授权

US07698664B2 Secure exchange of information in electronic design automation 有权
标题翻译：在电子设计自动化中安全交换信息
公开(公告)号：US07698664B2
公开(公告)日：2010-04-13
申请号：US11751511
申请日：2007-05-21
申请人： John G. Ferguson , Fedor G. Pikus , Kyohei Sakajiri , Laurence W. Grodd
发明人： John G. Ferguson , Fedor G. Pikus , Kyohei Sakajiri , Laurence W. Grodd
IPC分类号： G06F17/50 , G06F21/00 , H03K19/00 , H04N7/167 , H04L9/00 , G06Q40/00
CPC分类号： G06Q40/04 , H04L9/0838 , H04L2209/16
摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.
摘要翻译：这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。可能会生成错误报告，而不会泄露安全规则。

7. 发明申请

US20100023905A1 Critical Area Deterministic Sampling 审中-公开
标题翻译：关键区确定性抽样
公开(公告)号：US20100023905A1
公开(公告)日：2010-01-28
申请号：US12390354
申请日：2009-02-20
申请人： Fedor G. Pikus , John W. Stedman
发明人： Fedor G. Pikus , John W. Stedman
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A layout design for a portion of a microdevice design is partitioned into sections or “bins.” Next, a critical area value is estimated for one or more of the bins. One or more of these estimated bins is then selected for a more detailed analysis. After the estimated bins have been selected, a detailed critical area analysis of the selected bins is performed. Once the actual critical area for each of the estimated bins has been determined, the actual critical areas for selected estimated bins are correlated with those bin's corresponding estimated values. By correlating the actual critical areas of selected estimated bin to those bin's corresponding estimated values, a mapping function can be determined. After the mapping function has been determined, it is applied to the estimated values for each of the remaining bins of the layout design (i.e., the bins for which an actual critical area have not yet been determined) to obtain critical area information for the layout design. The layout design can then be modified based upon the obtained critical area information.
摘要翻译：微型设计设计的一部分的布局设计被划分为部分或“仓”。接下来，估计一个或多个箱的临界面积值。然后选择一个或多个这些估计的箱体进行更详细的分析。在选择了估计的料仓之后，对所选择的料仓进行详细的关键区域分析。一旦确定了每个估计仓的实际临界区域，则所选估计仓的实际关键区域与这些仓库的相应估计值相关。通过将所选择的估计bin的实际关键区域与这些bin的相应估计值相关联，可以确定映射函数。在确定映射函数之后，将其应用于布局设计的每个剩余箱的估计值（即，尚未确定实际临界区的箱），以获得布局的关键区域信息设计。然后可以基于获得的关键区域信息来修改布局设计。

8. 发明申请

US20090222927A1 Concealment of Information in Electronic Design Automation 审中-公开
标题翻译：电子设计自动化信息隐藏
公开(公告)号：US20090222927A1
公开(公告)日：2009-09-03
申请号：US12226943
申请日：2007-04-30
申请人： Fedor G. Pikus
发明人： Fedor G. Pikus
IPC分类号： G06F21/00 , G06F17/00
CPC分类号： G06F17/5081 , G06F21/6209 , G06F21/6227 , G09C5/00 , H04L9/0863 , H04L9/321
摘要： In one exemplary embodiment disclosed herein, an electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.
摘要翻译：在本文公开的一个示例性实施例中，电子设计自动化工具可以接收与电子设计自动化相关的信息，其包含诸如物理上保密的信息等安全信息，以及指示信息的安全部分的注释。电子设计自动化工具在接收到这样的信息时，可以识别包括与电子设计自动化相关的安全信息的信息的那些部分，并且解锁用于处理的安全信息。电子设计自动化工具可以处理至少一些安全的电子设计自动化信息，而不向未经授权的人员，工具，系统或其他方式泄漏安全信息，从而损害对该安全信息的保护。也就是说，设计自动化工具可以处理安全的电子设计自动化信息，使得安全信息在被处理时被隐藏，并且由处理安全信息产生的输出信息。

9. 发明申请

US20080189667A1 Model-based design verification 有权
标题翻译：基于模型的设计验证
公开(公告)号：US20080189667A1
公开(公告)日：2008-08-07
申请号：US11986564
申请日：2007-11-20
申请人： Fedor G. Pikus , David A. Abercrombie
发明人： Fedor G. Pikus , David A. Abercrombie
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.
摘要翻译：模拟设计规则检查工具分析微设计设计，例如集成电路设计，以识别共享指定关系的几何元素的出现。当工具识别这些几何元素的这种出现时，它将将这些几何元素相关联或“聚集”到一个可识别的单元中。对于几何元素的特定“簇”，模拟设计规则检查工具将确定用户所需的测量值或测量值。一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的功能。

10. 发明授权

US10643015B2 Properties in electronic design automation 有权
公开(公告)号：US10643015B2
公开(公告)日：2020-05-05
申请号：US11869720
申请日：2007-10-09
申请人： Fedor G. Pikus , Phillip A. Brooks , Gary S. Myron
发明人： Fedor G. Pikus , Phillip A. Brooks , Gary S. Myron
IPC分类号： G06F17/50 , G06F30/398 , G06F119/18
CPC分类号： G06F30/398 , G06F2119/18 , Y02P90/265
摘要： One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property's value is not dependent upon the value of any other properties. Alternately, a property may be a compound property, where the definition of the property's value incorporates another, previously-determined property value. Still further, a property may be an alternative property, where the property is assigned one value definition under a first set of conditions and assigned another value definition under a second set of conditions. A first electronic design automation process may generate one or more property values. The generated property values then can be passed to another electronic design automation process in the design analysis flow for its use.

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