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1. 发明授权

US07119369B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US07119369B2
公开(公告)日：2006-10-10
申请号：US10758059
申请日：2004-01-15
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.
摘要翻译：场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。

2. 发明授权

US06716687B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US06716687B2
公开(公告)日：2004-04-06
申请号：US10073723
申请日：2002-02-11
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L2184
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.
摘要翻译：场效应晶体管及其制造方法具有与其源/漏区分开形成的沟道区，并且具有介于沟道区和源/漏区之间的单晶材料。单晶材料包括单晶硅和硅 - 锗合金。

3. 发明申请

US20060091479A1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US20060091479A1
公开(公告)日：2006-05-04
申请号：US11305597
申请日：2005-12-16
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L29/76
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

4. 发明授权

US06448129B1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US06448129B1
公开(公告)日：2002-09-10
申请号：US09490261
申请日：2000-01-24
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

5. 发明授权

US07342273B2 Applying epitaxial silicon in disposable spacer flow 有权
标题翻译：在一次性间隔流中应用外延硅
公开(公告)号：US07342273B2
公开(公告)日：2008-03-11
申请号：US11305597
申请日：2005-12-16
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.
摘要翻译：一种通过以下步骤形成用于半导体存储器件的有源晶体管的工艺：在存储器阵列部分和外围部分中形成具有大致垂直侧壁的晶体管栅极; 将第一类导电掺杂剂注入限定为晶体管栅极的有源区域的暴露的硅中; 在所述晶体管栅极的大致垂直侧壁上形成临时氧化物间隔物; 在形成临时间隔物的步骤之后，将第二类型的导电掺杂剂注入暴露的硅区域以形成有源晶体管的源极/漏极区域; 在植入第二类导电掺杂剂的步骤之后，在暴露的硅区域上生长外延硅; 去除临时氧化物间隔物; 以及在晶体管栅极的大致垂直侧壁上形成永久性氮化物间隔物。

6. 发明授权

US07037775B2 Applying epitaxial silicon in disposable spacer flow 失效
公开(公告)号：US07037775B2
公开(公告)日：2006-05-02
申请号：US10861438
申请日：2004-06-03
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

7. 发明授权

US06756264B2 Applying epitaxial silicon in disposable spacer flow 失效
标题翻译：在一次性间隔流中应用外延硅
公开(公告)号：US06756264B2
公开(公告)日：2004-06-29
申请号：US10198924
申请日：2002-07-19
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.
摘要翻译：一种通过以下步骤形成用于半导体存储器件的有源晶体管的工艺：在存储器阵列部分和外围部分中形成具有大致垂直侧壁的晶体管栅极; 将第一类导电掺杂剂注入限定为晶体管栅极的有源区域的暴露的硅中; 在所述晶体管栅极的大致垂直侧壁上形成临时氧化物间隔物; 在形成临时间隔物的步骤之后，将第二类型的导电掺杂剂注入暴露的硅区域以形成有源晶体管的源极/漏极区域; 在植入第二类导电掺杂剂的步骤之后，在暴露的硅区域上生长外延硅; 去除临时氧化物间隔物; 以及在晶体管栅极的大致垂直侧壁上形成永久性氮化物间隔物。

8. 发明申请

US20050151198A1 Apparatus for increasing SRAM cell capacitance with metal fill 审中-公开
标题翻译：用于通过金属填充增加SRAM单元电容的装置
公开(公告)号：US20050151198A1
公开(公告)日：2005-07-14
申请号：US11057302
申请日：2005-02-11
申请人： Zhongze Wang , Chih-Chen Cho
发明人： Zhongze Wang , Chih-Chen Cho
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： G11C11/4125 , G11C11/412 , H01L21/76885 , H01L27/11 , H01L27/1104
摘要： A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.
摘要翻译：具有金属填充的静态随机存取存储器单元以形成用于增加存储单元的电容的电容器。更具体地说，一种半导体器件，包括具有形成在该结构的上表面上的上表面和接触表面的结构。介电材料在接触表面上与第一导电节点和延伸超出电介质材料的第二导电节点形成。电介质隔板围绕第一和第二导电节点形成，并且导电元件形成在电介质间隔件之间。导电元件和间隔件形成电容器而不实施附加的掩蔽步骤。

9. 发明授权

US06599789B1 Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US06599789B1
公开(公告)日：2003-07-29
申请号：US09713844
申请日：2000-11-15
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L2184
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

10. 发明授权

US06583518B2 Cross-diffusion resistant dual-polycide semiconductor structure and method 有权
公开(公告)号：US06583518B2
公开(公告)日：2003-06-24
申请号：US09945380
申请日：2001-08-31
申请人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
发明人： Jigish D. Trivedi , Zhongze Wang , Todd R. Abbott , Chih-Chen Cho
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.

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