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    • 7. 发明授权
    • Transistor with reduced parasitic capacitance
    • 降低寄生电容的晶体管
    • US08809962B2
    • 2014-08-19
    • US13218988
    • 2011-08-26
    • Yanxiang LiuJinping LiuMin DaiXiaodong Yang
    • Yanxiang LiuJinping LiuMin DaiXiaodong Yang
    • H01L29/78H01L21/336H01L29/66H01L29/49H01L29/51
    • H01L29/6653H01L29/4966H01L29/4983H01L29/513H01L29/517H01L29/66545H01L29/66553H01L29/66628
    • Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
    • 具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。 实施例包括晶体管,其包括与替代金属栅电极间隔开的沟槽硅化物层,以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。 实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构,去除可移除栅极,在氮化物间隔物上形成高k材料层,在高k材料上形成金属氮化物层,填充开口 用绝缘材料,然后去除其一部分以形成凹槽,去除金属氮化物层和高k材料层,沉积SiO 2或低k材料层,并在剩余的凹槽中形成替换金属栅极。