专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090119085A1 METHOD AND SYSTEM FOR MODELING DYNAMIC BEHAVIOR OF A TRANSISTOR 有权
标题翻译：用于建模晶体管动态特性的方法和系统
公开(公告)号：US20090119085A1
公开(公告)日：2009-05-07
申请号：US11935969
申请日：2007-11-06
申请人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
发明人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.
摘要翻译：公开了用于建模晶体管的动态行为的方法和系统。该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

2. 发明授权

US09348957B1 Repetitive circuit simulation 有权
标题翻译：重复电路仿真
公开(公告)号：US09348957B1
公开(公告)日：2016-05-24
申请号：US13250541
申请日：2011-09-30
申请人： Zhihong Liu , Bruce W. McGaughy
发明人： Zhihong Liu , Bruce W. McGaughy
IPC分类号： G06F17/50 , G01R31/3185
CPC分类号： G06F17/5036 , G01R31/318583
摘要： Method and system are disclosed for repetitive circuit simulation. In one embodiment, a computer implemented method for performing multiple simulations of a circuit includes providing descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit, parsing the circuit in accordance with the descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit to form one or more circuit partitions, performing a first pass simulation of the one or more circuit partitions in accordance with a set of stimuli to generate a history of the first pass simulation, and performing subsequent simulation of the one or more circuit partitions using the history of the first pass simulation.
摘要翻译：公开了重复电路仿真的方法和系统。在一个实施例中，用于执行电路的多次模拟的计算机实现的方法包括提供电路的连接性，时刻，信号活动和统计参数的描述，根据连接性，时刻，信号活动和用于形成一个或多个电路分区的电路的统计参数，根据一组刺激来执行一个或多个电路分区的第一遍仿真以产生第一遍仿真的历史，以及执行下一个仿真更多的电路分区使用第一遍仿真的历史。

3. 发明授权

US07835890B2 Hot carrier circuit reliability simulation 有权
标题翻译：热载体电路可靠性仿真
公开(公告)号：US07835890B2
公开(公告)日：2010-11-16
申请号：US11867554
申请日：2007-10-04
申请人： Lifeng Wu , Zhihong Liu , Alvin I. Chen , Jeong Y. Choi , Bruce W. McGaughy
发明人： Lifeng Wu , Zhihong Liu , Alvin I. Chen , Jeong Y. Choi , Bruce W. McGaughy
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5036
摘要： The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.
摘要翻译：本发明涉及在老化电路中的可靠性模拟方法的许多改进，其操作已经通过热载波或其它效应而降级。可以在单次运行中模拟多个不同的电路应力时间。不同的老化标准可用于不同的电路块，电路块类型，器件，器件型号和器件类型。用户可以独立于模拟来指定所选择的电路块，电路块类型，设备，设备模型和设备类型的劣化。器件劣化可以在表中进行表征。可以量化连续降解水平。还描述了用于在网表中表示老化设备的技术，因为新设备通过连接在其终端之间的多个独立电流源来增强，以模拟设备中的老化的影响。还描述了使用具有年龄参数的设备型号卡。为了进一步提高电路可靠性仿真，采用逐步或多步老化代替标准的一步老化过程。这些功能中的许多可以嵌入在电路仿真器中。还呈现用户数据接口以实现这些技术，并且进一步允许用户输入其未在模拟器中呈现的设备模型。例如，一个专有的模型，例如NMOS中的衬底电流可以用SPICE仿真器使用不同的模型来模拟电路的老化。

4. 发明授权

US07933747B2 Method and system for simulating dynamic behavior of a transistor 有权
标题翻译：用于模拟晶体管动态特性的方法和系统
公开(公告)号：US07933747B2
公开(公告)日：2011-04-26
申请号：US11935969
申请日：2007-11-06
申请人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
发明人： Yutao Ma , Min-Chie Jeng , Bruce W. McGaughy , Lifeng Wu , Zhihong Liu
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.
摘要翻译：公开了用于建模晶体管的动态行为的方法和系统。该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

5. 发明授权

US07292968B2 Hot carrier circuit reliability simulation 有权
标题翻译：热载体电路可靠性仿真
公开(公告)号：US07292968B2
公开(公告)日：2007-11-06
申请号：US09832933
申请日：2001-04-11
申请人： Lifeng Wu , Zhihong Liu , Alvin I. Chen , Jeong Y. Choi , Bruce W. McGaughy
发明人： Lifeng Wu , Zhihong Liu , Alvin I. Chen , Jeong Y. Choi , Bruce W. McGaughy
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5036
摘要： The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.
摘要翻译：本发明涉及在老化电路中的可靠性模拟方法的许多改进，其操作已经通过热载波或其它效应而降级。可以在单次运行中模拟多个不同的电路应力时间。不同的老化标准可用于不同的电路块，电路块类型，器件，器件型号和器件类型。用户可以独立于模拟来指定所选择的电路块，电路块类型，设备，设备模型和设备类型的劣化。器件劣化可以在表中进行表征。可以量化连续降解水平。还描述了用于在网表中表示老化设备的技术，因为新设备通过连接在其终端之间的多个独立电流源来增强，以模拟设备中的老化的影响。还描述了使用具有年龄参数的设备型号卡。为了进一步提高电路可靠性仿真，采用逐步或多步老化代替标准的一步老化过程。这些功能中的许多可以嵌入在电路仿真器中。还呈现用户数据接口以实现这些技术，并且进一步允许用户输入其未在模拟器中呈现的设备模型。例如，一个专有的模型，例如NMOS中的衬底电流可以用SPICE仿真器使用不同的模型来模拟电路的老化。

6. 发明授权

US08428928B1 System and method for dynamically representing repetitive loads of a circuit during simulation 有权
标题翻译：在仿真期间动态表示电路的重复负载的系统和方法
公开(公告)号：US08428928B1
公开(公告)日：2013-04-23
申请号：US10713728
申请日：2003-11-13
申请人： Bruce W. McGaughy
发明人： Bruce W. McGaughy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system for dynamically representing repetitive loads of a circuit during simulation includes a simulator module having one or more computer programs for 1) identifying one or more driver circuits for driving a plurality of repetitive receiver circuits, where each driver circuit has an output port and each repetitive receiver circuit has an input port, 2) creating a branch node driver for connecting the input ports of the plurality of repetitive receiver circuits and the output ports of the one or more driver circuits, 3) creating a shared load for representing aggregated input port loads of the plurality of receiver circuits having a substantially same isomorphic behavior, 4) creating a port connectivity interface for communicating changes of signal conditions between the output ports of the one or more driver circuits and the corresponding input ports of the plurality of repetitive receiver circuits, and 5) simulating the one or more driver circuits and the plurality of repetitive receiver circuits in accordance with the branch node driver, the shared load and the port connectivity interface.
摘要翻译：用于在仿真期间动态地表示电路的重复负载的系统包括具有一个或多个计算机程序的模拟器模块，用于1）识别用于驱动多个重复接收器电路的一个或多个驱动器电路，其中每个驱动器电路具有输出端口和每个重复接收电路具有输入端口，2）创建用于连接多个重复接收电路的输入端口和一个或多个驱动电路的输出端口的分支节点驱动器，3）创建用于表示聚合输入端口的共享负载多个接收器电路的负载具有基本相同的同构行为; 4）创建用于传送一个或多个驱动器电路的输出端口与多个重复接收器电路的相应输入端口之间的信号状态变化的端口连接接口，以及5）模拟一个或多个驱动器电路和多个重复r 收发电路按照分支节点驱动，共享负载和端口连接接口。

7. 发明授权

US07409328B1 System and method for communicating simulation solutions between circuit components in a hierarchical data structure 失效
标题翻译：用于在分层数据结构中的电路组件之间传递模拟解决方案的系统和方法
公开(公告)号：US07409328B1
公开(公告)日：2008-08-05
申请号：US10713754
申请日：2003-11-13
申请人： Bruce W. McGaughy , Jun Kong , Peter Frey , Jaideep Muhkerjee
发明人： Bruce W. McGaughy , Jun Kong , Peter Frey , Jaideep Muhkerjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that contains one or more driver leaf circuits and a second branch that also contains one or more receiver leaf circuits, where the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. The simulator module further includes computer programs for simulating operation of the one or more driver leaf circuits and the one or more receiver leaf circuits, together, without simulating operation of the third branch to determine a first set of changes in signal conditions shared by the one or more driver leaf circuits and the one or more receiver leaf circuits.
摘要翻译：用于在分层数据结构中的电路组件之间传递模拟解决方案的系统包括具有一个或多个计算机程序的模拟器模块，该计算机程序用于将该电路表示为分层布置的分支集，其包括根分支和逻辑上组织在一起的多个其他分支一张图。分层布置的分支集合包括包含一个或多个驱动器叶电路的第一分支和还包含一个或多个接收器叶电路的第二分支，其中第一分支和第二分支通过第三分支在图中互连，图中的分级水平高于第一和第二分支。模拟器模块还包括用于在不模拟第三分支的操作的情况下模拟一个或多个驱动器叶电路和一个或多个接收器叶电路的操作的计算机程序，以确定由该一个共享的信号条件的第一组变化或更多的驱动器叶电路和一个或多个接收器叶电路。

8. 发明授权

US07373289B2 Electrical isomorphism 有权
标题翻译：电同构
公开(公告)号：US07373289B2
公开(公告)日：2008-05-13
申请号：US10993687
申请日：2004-11-19
申请人： Bruce W. McGaughy , Wai Chung William Au , Baolin Yang
发明人： Bruce W. McGaughy , Wai Chung William Au , Baolin Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network. The method further includes simulating the first and second electrical networks using the single electrically isomorphic network.
摘要翻译：公开了用于确定两个电网之间的电同构的方法和系统。在一个实施例中，该方法包括将电路表示为分层布置的分支集合。分层布置的分支集合包括包括第一电网的第一分支和包括第二电网的第二分支，其中第一和第二分支在图中通过第三分支以更高层次级互连图比第一和第二分支。接下来，该方法确定第一和第二电网络是否是电同构网络。如果第一和第二电网被确定为电同构网络，则第一和第二电网由单个电同构网络表示。该方法还包括使用单个电同构网络来模拟第一和第二电网络。

9. 发明授权

US07143021B1 Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure 有权
标题翻译：有效地模拟具有分层结构的设计的模拟行为的系统和方法
公开(公告)号：US07143021B1
公开(公告)日：2006-11-28
申请号：US09969923
申请日：2001-10-03
申请人： Bruce W. McGaughy , Prashant Karhade , Peng Wan , Manish Singh
发明人： Bruce W. McGaughy , Prashant Karhade , Peng Wan , Manish Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits). If the handles (SH's) of two or more subcircuit parts point to a same, state-describing S-part, where the latter points to a merged I-circuit, and where the latter points to a merged T-circuit, then it can be determined by this that the respective subcircuit parts are both isomorphic and substantially iso-static and can therefore follow a commonly appointed leader. The disclosed system can be used with fully-flattened design definitions as well as with highly hierarchical design definitions.
摘要翻译：机器实现的模拟支持系统创建数据结构的层次结构，用于简化识别子拓扑，异构几何和等静态实例的子电路定义的任务。可以通过为他们指定一个模拟领导者并使用模拟领导者与各自的模拟模型结合来预测模拟领导者的行为来同时预测这种同构和异常静态实例的行为。然后，为追随者复制领导者的预测行为。在一个实施例中，状态描述S电路卡各自指向相应且可能合并的I电路卡。 I电路卡各自指向相应的并且可能合并的元件实例化卡（AG卡）以及相应且可能合并的互连拓扑描述卡（T形电路）。如果两个或多个子电路部分的手柄（SH）指向相同的状态描述S部分，后者指向合并的I电路，并且后者指向合并的T形电路，那么它可以由此确定各个子电路部件都是同构的并且基本上是等静电的，并且因此可以遵循通常指定的引导件。所公开的系统可以使用完全平坦的设计定义以及高度层次化的设计定义。

10. 发明授权

US08326591B1 Synchronized envelope and transient simulation of circuits 有权
标题翻译：电路的同步包络和瞬态仿真
公开(公告)号：US08326591B1
公开(公告)日：2012-12-04
申请号：US11941904
申请日：2007-11-16
申请人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
发明人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.
摘要翻译：在本发明的一个实施例中，公开了一种模拟电路的方法，包括将电路划分成多个块，所述多个块中的每一个是射频块或非射频块; 利用所述射频块执行第一仿真类型的第一仿真以产生所述射频块的输出波形; 对非射频块进行第二仿真类型的第二仿真，以产生第二仿真类型与第一仿真类型不同的非射频块的输出波形; 以及在一个或多个时间步骤一起同步所述第一仿真和所述第二仿真以产生所述电路的输出波形。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式