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1. 发明申请

US20130264609A1 Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof 审中-公开
标题翻译：共面Ge和III-V混合物的半导体结构及其制备方法
公开(公告)号：US20130264609A1
公开(公告)日：2013-10-10
申请号：US13636127
申请日：2012-05-16
申请人： Zengfeng Di , Jiantao Bian , Miao Zhang , Xi Wang
发明人： Zengfeng Di , Jiantao Bian , Miao Zhang , Xi Wang
IPC分类号： H01L29/66 , H01L29/778
CPC分类号： H01L29/66431 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/28264 , H01L21/8258 , H01L21/84 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/78
摘要： The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure.
摘要翻译：本发明提供了具有Ge和III-V族III族材料共面的混合物的半导体结构及其制备方法。具有Ge和III-V族半导体材料共面的非均匀集成半导体结构包括形成在体硅衬底上的至少一个Ge衬底，而另一衬底是形成在Ge半导体上的III-V族半导体材料。制备方法包括：在体硅衬底上制备Ge半导体层; 在Ge半导体层上制备III-V族III族半导体材料层; 进行第一光刻和蚀刻，以将图案化的窗口制成Ge层以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的杂化物的非均匀集成的半导体结构; 去除间隔物和接近间隔物的Ge层的缺陷部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge沟道PMOS和III-V族沟道NMOS的高性能CMOS器件。

2. 发明申请

US20130062696A1 SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof 审中-公开
标题翻译：具有共面锗和III-V杂化的SOI半导体结构及其制备方法
公开(公告)号：US20130062696A1
公开(公告)日：2013-03-14
申请号：US13636128
申请日：2012-05-16
申请人： Zengfeng Di , Jiantao Bian , Miao Zhang , Xi Wang
发明人： Zengfeng Di , Jiantao Bian , Miao Zhang , Xi Wang
IPC分类号： H01L27/12 , H01L21/20 , H01L21/84
CPC分类号： H01L21/84 , H01L21/8258
摘要： The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.
摘要翻译：本发明提供具有共面锗（Ge）和III-V的杂化物的SOI半导体结构及其制备方法。具有Ge和在绝缘体上共面的III-V族半导体材料的混合物的异质集成半导体结构包括形成在绝缘层上的至少一个Ge衬底，而另一衬底是形成在Ge上的III-V族半导体材料半导体。用于形成半导体结构的制备方法包括：制备全局Ge绝缘体衬底结构; 在Ge绝缘体衬底结构上制备III-V族III族半导体材料层; 第一次进行光刻和蚀刻，以形成图案化窗口到Ge层的上方以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的混合物的异质集成半导体结构; 去除间隔物和靠近隔离物的缺陷Ge层部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge PMOS和III-V NMOS的高性能CMOS器件。

3. 发明申请

US20150194338A1 Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer 有权
标题翻译：通过掺杂超薄层吸附绝缘体制备超薄材料的方法
公开(公告)号：US20150194338A1
公开(公告)日：2015-07-09
申请号：US13825079
申请日：2012-09-25
申请人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/762 , H01L21/306
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/30625
摘要： The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.
摘要翻译：本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料通过离子注入和粘合工艺制备。所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤电影，实现提高生产效率和降低生产成本的目标。

4. 发明申请

US20130221412A1 Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof 审中-公开
标题翻译：基于混合取向SOI和沟道应力的器件系统结构及其制备方法
公开(公告)号：US20130221412A1
公开(公告)日：2013-08-29
申请号：US13811269
申请日：2012-09-19
申请人： Jiantao Bian , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zengfeng Di , Miao Zhang
IPC分类号： H01L29/04 , H01L29/786 , H01L29/66
CPC分类号： H01L29/045 , H01L27/0922 , H01L27/1207 , H01L29/0692 , H01L29/0696 , H01L29/165 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/66772 , H01L29/7824 , H01L29/7835 , H01L29/78654
摘要： The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion. In this manner, a carrier mobility is improved, Rdson of a high-voltage device is reduced, and performance of devices are improved, thereby facilitating further improvement of integration and reduction of power consumption.
摘要翻译：本发明提供了一种基于混合取向SOI和沟道应力的器件系统结构及其制备方法。根据本发明提供的制备方法，首先制备（100）/（110）全局杂化取向SOI结构; 然后，在全局混合取向SOI结构上顺序生长松弛的硅 - 锗层和应变硅层之后，形成（110）外延图形窗口; 然后，在（110）外延图形窗口外延生长（110）硅层和非松弛硅 - 锗层之后，将图案化混合取向SOI结构的表面平面化; 然后形成用于隔离装置的隔离结构; 最后，在（110）衬底部分中制备P型高电压器件结构，在（100）衬底部分中制备N型高压器件结构和/或低电压器件结构。以这种方式，提高了载流子迁移率，降低了高电压装置的Rdson，提高了器件性能，从而进一步提高了集成度和降低了功耗。

5. 发明申请

US20140199825A1 SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF 有权
标题翻译：硅锗绝缘隧道场效应晶体管及其制备方法
公开(公告)号：US20140199825A1
公开(公告)日：2014-07-17
申请号：US13811268
申请日：2012-09-19
申请人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L21/02532 , H01L21/02617 , H01L29/165 , H01L29/66356 , H01L29/66431 , H01L29/7391
摘要： A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production.
摘要翻译：提供硅/锗（SiGe）异质结隧道场效应晶体管（TFET）及其制备方法，其中器件的源极区域在硅锗（GeGe）或Ge区域上制造，漏极区域在Si区域中制造器件，从而在确保低OFF状态电流的同时获得高导通状态电流。本地Ge氧化和浓缩技术用于在某些地区实施高Ge含量的硅锗绝缘体（SGOI）或锗绝缘体（GOI）。在高Ge含量的SGOI或GOI中，Ge含量可控制在50％〜100％之间。另外，膜厚可以从5nm到20nm的范围内控制，便于实现器件工艺。在SiGe或Ge和Si的氧化和浓缩过程中，在SiGe或Ge和Si之间形成具有梯度Ge含量的SiGe异质结结构，从而消除缺陷。根据本发明的制备方法具有与CMOS工艺兼容的简单工艺，并且适用于大规模工业生产。

6. 发明授权

US09230849B2 Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer 有权
标题翻译：通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法
公开(公告)号：US09230849B2
公开(公告)日：2016-01-05
申请号：US13825079
申请日：2012-09-25
申请人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Da Chen , Jiantao Bian , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/30 , H01L21/762 , H01L21/306
CPC分类号： H01L21/76254 , H01L21/30604 , H01L21/30625
摘要： The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.
摘要翻译：本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料通过离子注入和粘合工艺制备。所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤电影，实现提高生产效率和降低生产成本的目标。

7. 发明授权

US08501577B2 Preparation method for full-isolated SOI with hybrid crystal orientations 有权
标题翻译：具有杂化晶体取向的全隔离SOI的制备方法
公开(公告)号：US08501577B2
公开(公告)日：2013-08-06
申请号：US13636126
申请日：2012-05-16
申请人： Jiantao Bian , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zengfeng Di , Miao Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76283 , H01L21/823807 , H01L21/823878
摘要： A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC.
摘要翻译：公开了一种基于该方法的具有杂化晶体取向的完全隔离绝缘体（SOI）衬底的制备方法以及互补金属氧化物半导体（CMOS）集成电路（IC）的制备方法。在本发明中提供的具有混合晶体取向的全隔离SOI衬底的制备方法中，采用SiGe层作为具有第一晶体取向的外延虚拟衬底层，以形成应变顶部硅，其中第一个晶体取向; 采用多晶硅支撑材料作为连接顶部硅与第一晶体取向的支撑体和具有第二晶体取向的顶部硅，从而可以除去具有第一晶体取向的应变顶部硅以下的SiGe层，并且填充绝缘材料以形成绝缘掩埋层。在该方法中形成的顶部硅和绝缘掩埋层具有均匀且可控的厚度，窗口中形成的应变硅和窗外的顶部硅分别具有不同的晶体取向，从而为NMOS和PMOS分别提供更高的迁移率，从而提高CMOS IC的性能。

8. 发明申请

US20130071993A1 Preparation Method for Full-Isolated SOI with Hybrid Crystal Orientations 有权
标题翻译：具有混合晶体取向的全隔离SOI的制备方法
公开(公告)号：US20130071993A1
公开(公告)日：2013-03-21
申请号：US13636126
申请日：2012-05-16
申请人： Jiantao Bian , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zengfeng Di , Miao Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76283 , H01L21/823807 , H01L21/823878
摘要： A preparation method for a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations and a preparation method of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) based on the method are disclosed. In the preparation method for the full-isolated SOI substrate with hybrid crystal orientations provided in the present invention, a SiGe layer is adopted to serve as an epitaxial virtual substrate layer with a first crystal orientation, so as to form a strained top silicon with the first crystal orientation; a polysilicon supporting material is adopted to serve as a support for connecting the top silicon with the first crystal orientation and a top silicon with a second crystal orientation, so that the SiGe layer below the strained top silicon with the first crystal orientation may be removed, and an insulating material is filled to form an insulating buried layer. The top silicon and the insulating buried layer formed in the method have uniform and controllable thickness, the strained silicon formed in the window and the top silicon outside the window have different crystal orientations, so as to provide higher mobility for the NMOS and the PMOS respectively, thereby improving the performance of the CMOS IC.
摘要翻译：公开了一种基于该方法的具有杂化晶体取向的完全隔离绝缘体（SOI）衬底的制备方法和基于该互补金属氧化物半导体（CMOS）集成电路（IC）的制备方法。在本发明中提供的具有混合晶体取向的全隔离SOI衬底的制备方法中，采用SiGe层作为具有第一晶体取向的外延虚拟衬底层，以形成应变顶部硅，其中第一个晶体取向; 采用多晶硅支撑材料作为连接顶部硅与第一晶体取向的支撑体和具有第二晶体取向的顶部硅，从而可以除去具有第一晶体取向的应变顶部硅以下的SiGe层，并且填充绝缘材料以形成绝缘掩埋层。在该方法中形成的顶部硅和绝缘掩埋层具有均匀且可控的厚度，窗口中形成的应变硅和窗外的顶部硅分别具有不同的晶体取向，从而为NMOS和PMOS分别提供更高的迁移率，从而提高CMOS IC的性能。

9. 发明授权

US08877608B2 Method for preparing GOI chip structure 有权
标题翻译：制备GOI芯片结构的方法
公开(公告)号：US08877608B2
公开(公告)日：2014-11-04
申请号：US13825010
申请日：2012-09-25
申请人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/46 , H01L21/762
CPC分类号： H01L21/76254
摘要： The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
摘要翻译：本发明提供了一种制备GOI芯片结构的方法，其中在该方法中，首先通过使用SMART CUT技术制造绝缘体上硅锗（SGOI）芯片结构，然后在SGOI上进行锗冷凝技术芯片结构，从而获得GOI芯片结构。由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错，因此GOI的穿透位错密度最终降低。本发明的技术简单，可以实现高质量的GOI芯片结构，并且锗冷凝技术得到极大改善。离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术，因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。

10. 发明申请

US20140004684A1 Method for Preparing GOI Chip Structure 有权
标题翻译：制备GOI芯片结构的方法
公开(公告)号：US20140004684A1
公开(公告)日：2014-01-02
申请号：US13825010
申请日：2012-09-25
申请人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
发明人： Zengfeng Di , Lin Ye , Zhongying Xue , Miao Zhang
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.
摘要翻译：本发明提供了一种制备GOI芯片结构的方法，其中在该方法中，首先通过使用Smart-Cut技术制造绝缘体上的SiGe（SGOI）芯片结构，然后在 SGOI芯片结构，从而获得GOI芯片结构。由于采用智能切割技术制成的SGOI基本上在SGOI / BOX接口中没有错配位错，因此GOI的穿透位错密度最终降低。本发明的技术简单，可以实现高质量的GOI芯片结构，并且锗冷凝技术得到极大改善。离子注入技术和退火技术在目前的半导体工业中是相当成熟的技术，因此这种制备方法大大提高了半导体工业中锗浓缩技术的广泛应用的可能性。

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