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1. 发明授权

US07020789B2 Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands 失效
标题翻译：处理器核心和方法通过在微指令具有窄操作数时不使用专用于宽操作数的组件来降低功耗
公开(公告)号：US07020789B2
公开(公告)日：2006-03-28
申请号：US10334115
申请日：2002-12-31
申请人： Zeev Sperber , Ittai Anati , Yuval Bustan , Sagi Lahav
发明人： Zeev Sperber , Ittai Anati , Yuval Bustan , Sagi Lahav
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F1/3203 , G06F1/3243 , G06F9/384 , Y02D10/152 , Y02D50/20
摘要： In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.
摘要翻译：在本发明的一些实施例中，处理器核心的一个或多个元件可以接收指示微指令的操作数窄的信号，例如小于或等于32位。响应于该信号，能够处理超过32位数据（例如，操作数或结果）的处理器核心元件的一个或多个组件可以像处理仅32位的数据一样起作用。

2. 发明申请

US20070088965A1 Processor and methods to reduce power consumption of processor components 审中-公开
公开(公告)号：US20070088965A1
公开(公告)日：2007-04-19
申请号：US11637064
申请日：2006-12-12
申请人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
发明人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
IPC分类号： G06F1/00
CPC分类号： G06F1/3228 , G06F1/3203
摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

3. 发明授权

US07167989B2 Processor and methods to reduce power consumption of processor components 失效
标题翻译：处理器和方法来降低处理器组件的功耗
公开(公告)号：US07167989B2
公开(公告)日：2007-01-23
申请号：US10682892
申请日：2003-10-14
申请人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
发明人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
IPC分类号： G06F9/00
CPC分类号： G06F1/3228 , G06F1/3203
摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.
摘要翻译：可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下运行，后者用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

4. 发明申请

US20050081067A1 Processor and methods to reduce power consumption of procesor components 失效
标题翻译：处理器和减少处理器组件功耗的方法
公开(公告)号：US20050081067A1
公开(公告)日：2005-04-14
申请号：US10682892
申请日：2003-10-14
申请人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
发明人： Zeev Sperber , Ittai Anati , Ofer Sierra , Asi Joseph , Sagi Lahav
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3228 , G06F1/3203
摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.
摘要翻译：可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下工作，后者用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

5. 发明申请

US20090327657A1 GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops) 审中-公开
标题翻译：生成和执行包含多个微操作的依赖性控制流（uop）
公开(公告)号：US20090327657A1
公开(公告)日：2009-12-31
申请号：US12146390
申请日：2008-06-25
申请人： Zeev Sperber , Sagi Lahav , Guy Patkin , Simon Rubanovich , Amit Gradstein , Yuval Bustan
发明人： Zeev Sperber , Sagi Lahav , Guy Patkin , Simon Rubanovich , Amit Gradstein , Yuval Bustan
IPC分类号： G06F9/22
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3838 , G06F9/384 , G06F9/3853
摘要： A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.
摘要翻译：执行无序（OOO）处理的处理器，其中保留站（RS）可以生成并处理包括具有特定的基于时钟的调度方案的多个微操作（uop）的依赖性控制流。 RS可以将两个或更多个uops组合成单个RS条目，或者在两个或更多个RS条目之间建立直接连接。 RS可以通过组合来自两个或更多个uops的源来允许多于两个源值与单个RS相关联。可以提供一个或多个执行单元来执行由uops定义的功能。执行单元可以在给定的时间点接收多于两个的源，并且在不同端口上产生两个或更多个结果。

6. 发明授权

US07430656B2 System and method of converting data formats and communicating between execution units 有权
标题翻译：转换数据格式和执行单元之间的通信的系统和方法
公开(公告)号：US07430656B2
公开(公告)日：2008-09-30
申请号：US10334114
申请日：2002-12-31
申请人： Zeev Sperber , Ittai Anati , Oded Liron , Mohammad Abdallah
发明人： Zeev Sperber , Ittai Anati , Oded Liron , Mohammad Abdallah
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F7/00
CPC分类号： G06F9/30014 , G06F9/226 , G06F9/30025 , G06F9/30036 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.
摘要翻译：一种方法和系统，包括以多类型指令集体系结构中的执行单元之间的架构格式发送数据，并且以结构格式将接收的数据转换为内部格式，并以内部格式输出的数据基于操作代码和微指令的数据类型。

7. 发明申请

US20070038844A1 Technique to combine instructions 有权
标题翻译：技术结合说明
公开(公告)号：US20070038844A1
公开(公告)日：2007-02-15
申请号：US11200777
申请日：2005-08-09
申请人： Robert Valentine , Ittai Anati , Zeev Sperber , Ido Oziel , Gregory Pribush , Amir Leibovitz
发明人： Robert Valentine , Ittai Anati , Zeev Sperber , Ido Oziel , Gregory Pribush , Amir Leibovitz
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3863
摘要： A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.
摘要翻译：微操作（uop）融合技术。更具体地说，本发明的实施例涉及一种融合来自两个或更多个指令的两个或更多个uop的技术。

8. 发明授权

US07451294B2 Apparatus and method for two micro-operation flow using source override 失效
标题翻译：使用源超控的两个微操作流的装置和方法
公开(公告)号：US07451294B2
公开(公告)日：2008-11-11
申请号：US10631629
申请日：2003-07-30
申请人： Zeev Sperber , Yuval Bustan , Robert Valentine
发明人： Zeev Sperber , Yuval Bustan , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.
摘要翻译：一种使用源超控的两个微操作流的方法和装置。在一个实施例中，该方法包括识别具有一个或多个流单个指令多个数据扩展类型操作数的宏指令。一旦接收到，宏指令被解码成第一微操作（uop）和第二uop。一旦被解码，如果第一微操作更新与微操作的逻辑源寄存器匹配的逻辑目标寄存器，则信号被断言以禁用源操作数覆盖逻辑。否则，当在相同的时钟周期中检测到具有匹配逻辑源和目标寄存器的UOP时，互源替代是激活的并由寄存器别名表（RAT）执行。这样，具有128位操作数的宏指令可以在64位实现中使用例如两个uOP（一个用于下半部分，一个用于上半部分）来处理，同时保持原始指令的原子性。

9. 发明授权

US06920546B2 Fusion of processor micro-operations 有权
标题翻译：处理器微操作的融合
公开(公告)号：US06920546B2
公开(公告)日：2005-07-19
申请号：US10217033
申请日：2002-08-13
申请人： Simcha Gochman , Ittai Anati , Zeev Sperber , Robert Valentine
发明人： Simcha Gochman , Ittai Anati , Zeev Sperber , Robert Valentine
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/383
摘要： Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.
摘要翻译：方法和系统提供将多个操作融合到单个微操作（uop）中。解码宏指令的方法提供将与第一操作有关的数据从宏指令传送到uop。 uop将由处理器的执行系统执行。该方法还提供将与第二操作有关的数据从宏指令传送到uop。

10. 发明申请

US20060095731A1 Method and apparatus for avoiding read port assignment of a reorder buffer 审中-公开
标题翻译：避免重新排序缓冲区的读取端口分配的方法和装置
公开(公告)号：US20060095731A1
公开(公告)日：2006-05-04
申请号：US10932088
申请日：2004-09-02
申请人： Yuval Bustan , Asi Joseph , Guillermo Savransky , Zeev Sperber
发明人： Yuval Bustan , Asi Joseph , Guillermo Savransky , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： An out-of-order subsystem of a processor includes a register alias table and allocation (RAT/ALLOC) unit, a reservation station (RS) and a reorder buffer (ROB). Destination identifiers of one or more execution results that are not yet stored in any register file of the ROB may be compared to source identifiers of operands of micro-operations that are being issued to the RS. Each execution result corresponding to a destination identifier that matches one of the source identifiers is retrieved from a data path external to the ROB and routed to an appropriate port of the RS for an operand corresponding to the source identifier so that the RAT/ALLOC unit does not need to allocate a read port of the ROB for the RS to read the execution result.
摘要翻译：处理器的乱序子系统包括寄存器别名表和分配（RAT / ALLOC）单元，保留站（RS）和重排序缓冲器（ROB）。还没有存储在ROB的任何寄存器文件中的一个或多个执行结果的目的地标识符可以与正在发布到RS的微操作的操作数的源标识符进行比较。对应于与源标识符之一匹配的目的地标识符的每个执行结果从ROB外部的数据路径检索，并被路由到与源标识符相对应的操作数的RS的适当端口，使得RAT / ALLOC单元不需要分配ROB的读端口来读取执行结果。

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