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1. 发明申请

US20090327657A1 GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops) 审中-公开
标题翻译：生成和执行包含多个微操作的依赖性控制流（uop）
公开(公告)号：US20090327657A1
公开(公告)日：2009-12-31
申请号：US12146390
申请日：2008-06-25
申请人： Zeev Sperber , Sagi Lahav , Guy Patkin , Simon Rubanovich , Amit Gradstein , Yuval Bustan
发明人： Zeev Sperber , Sagi Lahav , Guy Patkin , Simon Rubanovich , Amit Gradstein , Yuval Bustan
IPC分类号： G06F9/22
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3838 , G06F9/384 , G06F9/3853
摘要： A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.
摘要翻译：执行无序（OOO）处理的处理器，其中保留站（RS）可以生成并处理包括具有特定的基于时钟的调度方案的多个微操作（uop）的依赖性控制流。 RS可以将两个或更多个uops组合成单个RS条目，或者在两个或更多个RS条目之间建立直接连接。 RS可以通过组合来自两个或更多个uops的源来允许多于两个源值与单个RS相关联。可以提供一个或多个执行单元来执行由uops定义的功能。执行单元可以在给定的时间点接收多于两个的源，并且在不同端口上产生两个或更多个结果。

2. 发明申请

US20140379773A1 FUSED MULTIPLY ADD OPERATIONS USING BIT MASKS 有权
标题翻译：使用位掩码的多功能加密操作
公开(公告)号：US20140379773A1
公开(公告)日：2014-12-25
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/485 , G06F7/487
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

3. 发明申请

US20140201502A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A BUTTERFLY HORIZONTAL AND CROSS ADD OR SUBSTRACT IN RESPONSE TO A SINGLE INSTRUCTION 有权
标题翻译：系统，设备和方法，用于执行水平和横向添加或影响单一指令
公开(公告)号：US20140201502A1
公开(公告)日：2014-07-17
申请号：US13992236
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F17/142
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described.
摘要翻译：用于在计算机处理器中执行向量包装蝶形水平交叉加法或减法的系统，装置和方法响应于包括目的地向量寄存器操作数的单向量包装蝶式水平交叉加减法指令，源描述向量寄存器操作数，立即数和操作码。

4. 发明授权

US09582464B2 Systems, apparatuses, and methods for performing a double blocked sum of absolute differences 有权
标题翻译：用于执行绝对差异的双重阻塞和的系统，装置和方法
公开(公告)号：US09582464B2
公开(公告)日：2017-02-28
申请号：US13992229
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F7/38 , G06F9/302 , G06F15/78 , G06F9/30 , G06F7/544 , G06F9/38 , G06F7/50
CPC分类号： G06F9/3001 , G06F7/50 , G06F7/544 , G06F9/30036 , G06F9/3836 , G06F9/3877 , G06F15/78 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要翻译：用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二描述源操作数，立即数和操作码。

5. 发明授权

US09619226B2 Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction 有权
公开(公告)号：US09619226B2
公开(公告)日：2017-04-11
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/302 , G06F9/305 , G06F15/76 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.

6. 发明申请

US20140365747A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL PARTIAL SUM IN RESPONSE TO A SINGLE INSTRUCTION 有权
标题翻译：用于执行水平部分响应单一指令的系统，设备和方法
公开(公告)号：US20140365747A1
公开(公告)日：2014-12-11
申请号：US13977612
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
发明人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30101
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
摘要翻译：用于在计算机处理器中执行的系统，装置和方法的实施例，响应于包括目的地向量寄存器操作数，源向量寄存器操作数和操作码的单向量压缩水平和指令，执行压缩数据元素的水平部分和被描述。

7. 发明申请

US20140188967A1 Leading Change Anticipator Logic 有权
标题翻译：领先的变革预期逻辑
公开(公告)号：US20140188967A1
公开(公告)日：2014-07-03
申请号：US13729421
申请日：2012-12-28
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F17/10
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： In one embodiment, a processor includes at least one floating point unit. The at least one floating point unit may include an adder, leading change anticipator (LCA) logic, and a shifter. The adder may be to add a first operand X and a second operand Y to obtain an output operand having a bit length n. The LCA logic may be to: for each bit position i from n−1 to 1, obtain a set of propagation values and a set of bit values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values. The shifter may be to normalize the output operand based on the LCA mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个浮点单元。所述至少一个浮点单元可以包括加法器，引导改变预测器（LCA）逻辑和移位器。加法器可以添加第一操作数X和第二操作数Y以获得具有位长度n的输出操作数。 LCA逻辑可以是：对于从n-1到1的每个比特位置i，基于第一操作数X和第二操作数Y获得一组传播值和一组比特值; 并且基于传播值集合和位值集合来生成LCA掩码。移位器可以是基于LCA掩码来规范化输出操作数。描述和要求保护其他实施例。

8. 发明申请

US20140082333A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS 审中-公开
标题翻译：用于执行两个矢量寄存器的包装数据元素之间的绝对差分计算的系统，设备和方法
公开(公告)号：US20140082333A1
公开(公告)日：2014-03-20
申请号：US13996849
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F17/10
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor absolute difference calculation in response to a single vector packed absolute difference instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
摘要翻译：描述了响应于包括第一和第二源向量寄存器操作数，目的向量寄存器操作数和操作码的单向量压缩绝对差指令在计算机处理器中执行绝对差计算的系统，装置和方法的实施例。

9. 发明申请

US20120166509A1 Performing Reciprocal Instructions With High Accuracy 有权
标题翻译：以高精度执行互惠指令
公开(公告)号：US20120166509A1
公开(公告)日：2012-06-28
申请号：US12976359
申请日：2010-12-22
申请人： Zeev Sperber , Cristina S. Anderson , Benny Eitan , Simon Rubanovich , Amit Gradstein
发明人： Zeev Sperber , Cristina S. Anderson , Benny Eitan , Simon Rubanovich , Amit Gradstein
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F9/30014 , G06F2207/5356 , G06F2207/5521
摘要： In one embodiment, the present invention includes a method for receiving a reciprocal instruction and an operand in a processor, accessing an entry of a lookup table based on a portion of the operand and the instruction, generating an encoder output based on a type of the reciprocal instruction and whether the reciprocal instruction is a legacy instruction, and selecting portions of the lookup table entry and input operand to be provided to a reciprocal logic unit based on the encoder output. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在处理器中接收互逆指令和操作数的方法，其基于所述操作数和所述指令的一部分访问查找表的条目，基于所述操作数的类型生成编码器输出互逆指令以及互易指令是否是遗留指令，以及基于编码器输出来选择要提供给倒数逻辑单元的查找表项和输入操作数的部分。描述和要求保护其他实施例。

10. 发明授权

US09542154B2 Fused multiply add operations using bit masks 有权
标题翻译：融合乘法使用位掩码添加操作
公开(公告)号：US09542154B2
公开(公告)日：2017-01-10
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/544 , G06F7/76
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

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