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1. 发明申请

US20100287343A1 CONTENTION FREE PARALLEL ACCESS SYSTEM AND A METHOD FOR CONTENTION FREE PARALLEL ACCESS TO A GROUP OF MEMORY BANKS 有权
标题翻译：内容自由并行访问系统和一种可以自由并行访问一组存储库的方法
公开(公告)号：US20100287343A1
公开(公告)日：2010-11-11
申请号：US12812032
申请日：2008-01-21
申请人： Yuval Neeman , Ron Bercovich , Guy Drory , Dror Gilad , Aviel Livay , Yonatan Naor
发明人： Yuval Neeman , Ron Bercovich , Guy Drory , Dror Gilad , Aviel Livay , Yonatan Naor
IPC分类号： G06F12/06
CPC分类号： H03M13/2771 , H03M13/2714 , H03M13/2725 , H03M13/275 , H03M13/2957 , H03M13/6566
摘要： A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element from an odd memory unit of a pair of memory banks and fetches a second information element from an even memory unit of the pair of memory banks; wherein the first and second information elements are two consecutive interleaved address information elements.
摘要翻译：一种并行接入系统，包括：一组包含N个处理实体的处理实体; 其中N是超过1的正整数; 一组存储K个信息元素的记忆库; 其中所述存储体组包括N对单个存取存储体; 每对存储体组包括偶数存储体和奇数存储体; 其中每对存储器组存储K / N个信息元素的子集; 其中每对存储器组的偶数存储体存储K / N个信息元素的某个子集的偶数地址信息元素，并且每对存储器组的奇数存储体组存储该特定子集的奇数地址信息元素的K / N信息要素; 其中K / N是偶数正整数; 以及耦合到所述一组处理实体和所述存储体组的非阻塞互连; 其中在每个读取周期期间，所述处理实体组中的每个处理实体从一对存储器组的奇数存储器单元中提取第一信息元素，并从所述一对存储器组的偶数存储器单元中提取第二信息元素; 其中所述第一和第二信息元素是两个连续的交错地址信息元素。

2. 发明授权

US08627022B2 Contention free parallel access system and a method for contention free parallel access to a group of memory banks 有权
标题翻译：无争用的并行访问系统和一种无争用并行访问一组存储体的方法
公开(公告)号：US08627022B2
公开(公告)日：2014-01-07
申请号：US12812032
申请日：2008-01-21
申请人： Yuval Neeman , Ron Bercovich , Guy Drory , Dror Gilad , Aviel Livay , Yonatan Naor
发明人： Yuval Neeman , Ron Bercovich , Guy Drory , Dror Gilad , Aviel Livay , Yonatan Naor
IPC分类号： G06F12/00
CPC分类号： H03M13/2771 , H03M13/2714 , H03M13/2725 , H03M13/275 , H03M13/2957 , H03M13/6566
摘要： A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element from an odd memory unit of a pair of memory banks and fetches a second information element from an even memory unit of the pair of memory banks; wherein the first and second information elements are two consecutive interleaved address information elements.
摘要翻译：一种并行接入系统，包括：一组包含N个处理实体的处理实体; 其中N是超过1的正整数; 一组存储K个信息元素的记忆库; 其中所述存储体组包括N对单个存取存储体; 每对存储体组包括偶数存储体和奇数存储体; 其中每对存储器组存储K / N个信息元素的子集; 其中每对存储器组的偶数存储体存储K / N个信息元素的某个子集的偶数地址信息元素，并且每对存储器组的奇数存储体组存储该特定子集的奇数地址信息元素的K / N信息要素; 其中K / N是偶数正整数; 以及耦合到所述一组处理实体和所述存储体组的非阻塞互连; 其中在每个读取周期期间，所述处理实体组中的每个处理实体从一对存储器组的奇数存储器单元中提取第一信息元素，并从所述一对存储器组的偶数存储器单元中提取第二信息元素; 其中所述第一和第二信息元素是两个连续的交错地址信息元素。

3. 发明授权

US08171384B2 Device having turbo decoding capabilities and a method for turbo decoding 有权
标题翻译：具有turbo解码能力的装置和用于turbo解码的方法
公开(公告)号：US08171384B2
公开(公告)日：2012-05-01
申请号：US12163638
申请日：2008-06-27
申请人： Guy Drory , Ron Bercovich , Yosef Kazaz , Aviel Livay , Yonatan Naor , Yuval Neeman
发明人： Guy Drory , Ron Bercovich , Yosef Kazaz , Aviel Livay , Yonatan Naor , Yuval Neeman
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/3905
摘要： A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.
摘要翻译：一种用于turbo解码的设备和方法，所述方法包括执行turbo解码过程的多次迭代，直到turbo解码过程完成; 其中所述执行包括重复以下阶段：（i）通过在先前迭代中计算的至少一个对应状态度量来初始化turbo解码过程的当前迭代的信道数据块的多个窗口的至少一个状态度量 turbo解码过程; 以及（ii）在当前迭代期间并行地计算多个窗口的至少前向状态度量和向后状态度量。

4. 发明申请

US20090327834A1 DEVICE HAVING TURBO DECODING CAPABILITIES AND A METHOD FOR TURBO DECODING 有权
标题翻译：具有涡轮解码能力的装置和用于涡轮解码的方法
公开(公告)号：US20090327834A1
公开(公告)日：2009-12-31
申请号：US12163638
申请日：2008-06-27
申请人： Guy Drory , Ron Bercovich , Yosef Kazaz , Aviel Livay , Yonatan Naor , Yuval Neeman
发明人： Guy Drory , Ron Bercovich , Yosef Kazaz , Aviel Livay , Yonatan Naor , Yuval Neeman
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/2957 , H03M13/3905
摘要： A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.
摘要翻译：一种用于turbo解码的设备和方法，所述方法包括执行turbo解码过程的多次迭代，直到turbo解码过程完成; 其中所述执行包括重复以下阶段：（i）通过在先前迭代中计算的至少一个对应状态度量来初始化turbo解码过程的当前迭代的信道数据块的多个窗口的至少一个状态度量 turbo解码过程; 以及（ii）在当前迭代期间并行地计算多个窗口的至少前向状态度量和向后状态度量。

5. 发明授权

US08413033B2 Device and method for calculating backward state metrics of a trellis 有权
标题翻译：用于计算网格的后向状态度量的装置和方法
公开(公告)号：US08413033B2
公开(公告)日：2013-04-02
申请号：US12509276
申请日：2009-07-24
申请人： Guy Drory , Ron Bercovich , Aviel Livay , Ilia Moskovich , Yuval Neeman
发明人： Guy Drory , Ron Bercovich , Aviel Livay , Ilia Moskovich , Yuval Neeman
IPC分类号： H03M13/00
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/395 , H03M13/6356 , H03M13/6525 , H03M13/6558
摘要： A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.
摘要翻译：一种用于计算网格的后向状态度量的方法，所述方法包括：对网格的至少一个时间实例的多个状态的后向状态矩阵进行基数K计算; 以及对所述网格的至少另一个时间实例的多个状态的后向状态矩阵进行基数-J计算; 其中K与J.

6. 发明授权

US08200733B1 Device having interleaving capabilities and a method for applying an interleaving function 有权
标题翻译：具有交织能力的装置和应用交织功能的方法
公开(公告)号：US08200733B1
公开(公告)日：2012-06-12
申请号：US12102996
申请日：2008-04-15
申请人： Yuval Neeman , Ron Berkovich , Guy Drory , Gilad Dror , Aviel Livay , Yonatan Naor
发明人： Yuval Neeman , Ron Berkovich , Guy Drory , Gilad Dror , Aviel Livay , Yonatan Naor
IPC分类号： G06F7/38
CPC分类号： H04L1/0071 , H03M13/2739 , H03M13/2775 , H03M13/2957 , H03M13/3972 , H03M13/6525
摘要： A method and a device having interleaving capabilities, the device comprises a first interleaver; the first interleaver comprises a first register, a second register, a first adder and a second adder; wherein the first register is coupled to the first adder and to the second adder; wherein the second register is coupled to the second adder; wherein the first adder is adapted to add a current first register value to a first coefficient to provide a next first register value that is stored at the first register; wherein the second adder is adapted to add a current first register value to a second coefficient, to a third coefficient and to a current second register value to provide an interleaved output value.
摘要翻译：一种具有交织能力的方法和装置，所述装置包括第一交织器; 第一交织器包括第一寄存器，第二寄存器，第一加法器和第二加法器; 其中所述第一寄存器耦合到所述第一加法器和所述第二加法器; 其中所述第二寄存器耦合到所述第二加法器; 其中所述第一加法器适于将当前第一寄存器值添加到第一系数以提供存储在所述第一寄存器的下一个第一寄存器值; 其中所述第二加法器适于将当前第一寄存器值添加到第二系数到第三系数和当前第二寄存器值以提供交错输出值。

7. 发明申请

US20110019781A1 DEVICE AND METHOD FOR CALCULATING BACKWARD STATE METRICS OF A TRELLIS 有权
标题翻译：用于计算TRELLIS的后向状态度量的装置和方法
公开(公告)号：US20110019781A1
公开(公告)日：2011-01-27
申请号：US12509276
申请日：2009-07-24
申请人： Guy Drory , Ron Bercovich , Aviel Livay , Ilia Moskovich , Yuval Neeman
发明人： Guy Drory , Ron Bercovich , Aviel Livay , Ilia Moskovich , Yuval Neeman
IPC分类号： H04L27/06 , H03M13/03
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/395 , H03M13/6356 , H03M13/6525 , H03M13/6558
摘要： A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.
摘要翻译：一种用于计算网格的后向状态度量的方法，所述方法包括：对网格的至少一个时间实例的多个状态的后向状态矩阵进行基数K计算; 以及对所述网格的至少另一个时间实例的多个状态的后向状态矩阵进行基数-J计算; 其中K与J.

8. 发明授权

US08595584B2 Method and apparatus for interleaving a data stream using quadrature permutation polynomial functions (QPP) 有权
标题翻译：使用正交置换多项式函数（QPP）来交织数据流的方法和装置
公开(公告)号：US08595584B2
公开(公告)日：2013-11-26
申请号：US12990865
申请日：2008-05-19
申请人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
发明人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/2957 , H03M13/6525
摘要： A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
摘要翻译：一种包括处理逻辑的半导体器件。处理逻辑被配置为配置交织器逻辑以根据正交置换多项式函数重新排序数据流的数据符号。所述处理逻辑还被配置为：将由所述QPP功能定义的循环组划分成一组子组，所述一组子组能够由一组线性函数定义; 导出定义子组的一组线性函数的反函数; 并且配置交织器逻辑，以基于定义的线性函数集合的反函数将数据流的数据符号加载到缓冲器中，该缓冲器位于对应于表示QPP函数的反函数的循环数组的缓冲器内的位置子组。

9. 发明申请

US20110060963A1 METHOD AND APPARATUS FOR INTERLEAVING A DATA STREAM USING QUADRATURE PERMUTATION POLYNOMIAL FUNCTIONS (QPP) 有权
标题翻译：用于使用平移多普勒函数（QPP）来交换数据流的方法和装置
公开(公告)号：US20110060963A1
公开(公告)日：2011-03-10
申请号：US12990865
申请日：2008-05-19
申请人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
发明人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
IPC分类号： H03M13/07 , H03M13/29 , G06F11/10
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/2957 , H03M13/6525
摘要： A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
摘要翻译：一种包括处理逻辑的半导体器件。处理逻辑被配置为配置交织器逻辑以根据正交置换多项式函数重新排序数据流的数据符号。所述处理逻辑还被配置为：将由所述QPP功能定义的循环组划分成一组子组，所述一组子组能够由一组线性函数定义; 导出定义子组的一组线性函数的反函数; 并且配置交织器逻辑，以基于定义的线性函数集合的反函数将数据流的数据符号加载到缓冲器中，该缓冲器位于对应于表示QPP函数的反函数的循环数组的缓冲器内的位置子组。

10. 发明授权

US07760114B2 System and a method for generating an interleaved output during a decoding of a data block 失效
标题翻译：系统和在数据块的解码期间产生交错输出的方法
公开(公告)号：US07760114B2
公开(公告)日：2010-07-20
申请号：US12261606
申请日：2008-10-30
申请人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
发明人： Yuval Neeman , Guy Drory , Aviel Livay , Inbar Schori
IPC分类号： H03M7/00
CPC分类号： H04L9/0631
摘要： A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.
摘要翻译：一种用于在数据块的解码期间产生交错输出的方法，所述方法包括：（i）响应于行指示符，选择行寄存器和乘法因子以提供所选择的行寄存器和选择的乘法因子; 其中所选择的乘法因子响应于所述数据块的大小; （ii）将存储在所选择的行寄存器中的值乘以所选乘法因子以提供中间结果; （iii）对中间结果执行模P运算以提供置换结果; 其中所述排列结果和存储在所选择的行寄存器中的值是相同排列的相邻元素; 其中P响应于所述数据块的大小; （iv）将排列的结果写入所选择的行寄存器; 和（v）输出响应于所述置换结果选择的数据块元素。

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