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    • 4. 发明授权
    • Receiving circuit and optical signal receiving circuit
    • 接收电路和光信号接收电路
    • US07809285B2
    • 2010-10-05
    • US11662090
    • 2005-08-29
    • Kazuko NishimuraHiroshi Kimura
    • Kazuko NishimuraHiroshi Kimura
    • H04B10/06
    • H03F3/08H03F1/08H03F2200/78H03G3/3084
    • A receiving circuit comprises a transimpedance amplifier 3 including an inversion amplifier 2 for amplifying an input current IN, and a feedback resistance R1 connected between an input and an output of the inversion amplifier 2, a comparison circuit 4 for comparing an output OUT of the transimpedance amplifier 3 with a certain desired reference value, and outputting a result of the comparison, and a control circuit for holding the comparison result, and generating an AGC signal 20 for adjusting a gain of the transimpedance amplifier 3. The transimpedance amplifier 20 has a function capable of gain adjustment in accordance with the input AGC signal 20. The control circuit 5 performs gain adjustment until the output OUT of the transimpedance amplifier 3 exceeds the reference value so that an appropriate gain is obtained. Therefore, even when an input has a wide dynamic range, it is possible to prevent signal saturation and a distortion in output waveform in the transimpedance amplifier, so that appropriate reception can be invariably performed and a signal having a stable duty can be output.
    • 接收电路包括跨阻抗放大器3,其包括用于放大输入电流IN的反相放大器2和连接在反相放大器2的输入和输出端之间的反馈电阻R1,比较电路4,用于比较跨阻抗的输出OUT 具有一定的期望参考值的放大器3,并输出比较结果,以及用于保持比较结果的控制电路,并产生用于调整跨阻抗放大器3的增益的AGC信号20.跨阻放大器20具有功能 能够根据输入的AGC信号20进行增益调整。控制电路5进行增益调整,直到跨阻抗放大器3的输出OUT超过参考值,从而获得适当的增益。 因此,即使当输入具有宽动态范围时,也可以防止跨阻放大器中的信号饱和和输出波形的失真,使得可以不间断地执行适当的接收,并且可以输出具有稳定占空比的信号。
    • 5. 发明申请
    • Receiving Circuit and Optical Signal Receiving Circuit
    • 接收电路和光信号接收电路
    • US20080056732A1
    • 2008-03-06
    • US11662090
    • 2005-08-29
    • Kazuko NishimuraHiroshi Kimura
    • Kazuko NishimuraHiroshi Kimura
    • H04B10/06
    • H03F3/08H03F1/08H03F2200/78H03G3/3084
    • A receiving circuit comprises a transimpedance amplifier 3 including an inversion amplifier 2 for amplifying an input current IN, and a feedback resistance R1 connected between an input and an output of the inversion amplifier 2, a comparison circuit 4 for comparing an output OUT of the transimpedance amplifier 3 with a certain desired reference value, and outputting a result of the comparison, and a control circuit for holding the comparison result, and generating an AGC signal 20 for adjusting a gain of the transimpedance amplifier 3. The transimpedance amplifier 20 has a function capable of gain adjustment in accordance with the input AGC signal 20. The control circuit 5 performs gain adjustment until the output OUT of the transimpedance amplifier 3 exceeds the reference value so that an appropriate gain is obtained. Therefore, even when an input has a wide dynamic range, it is possible to prevent signal satuation and a distortion in output waveform in the transimpedance amplifier, so that appropriate reception can be invariably performed and a signal having a stable duty can be output.
    • 接收电路包括跨阻抗放大器3,其包括用于放大输入电流IN的反相放大器2和连接在反相放大器2的输入和输出端之间的反馈电阻R 1,比较电路4, 具有一定期望参考值的跨阻抗放大器3,并输出比较结果,以及用于保持比较结果的控制电路,并产生用于调整跨阻抗放大器3的增益的AGC信号20.跨阻放大器20具有 功能,其能够根据输入的AGC信号20进行增益调整。控制电路5进行增益调整,直到跨阻抗放大器3的输出OUT超过参考值,从而获得适当的增益。 因此,即使当输入的动态范围宽时,也可以防止跨阻放大器的信号饱和和输出波形的失真,从而可以不间断地执行适当的接收,并且可以输出具有稳定占空比的信号。
    • 6. 发明授权
    • Current comparison type latch
    • 当前比较型锁存器
    • US06344761B2
    • 2002-02-05
    • US09819646
    • 2001-03-29
    • Kazuko NishimuraHiroshi Kimura
    • Kazuko NishimuraHiroshi Kimura
    • G11C706
    • H03K3/356113H03K3/356182
    • In a current comparison type latch, during a reset mode of the current comparison type latch where the clock signal is at the “L” level, transistors which are disposed along the current path extending from the high potential power supply line to the low potential power supply line are turned OFF while transistors which connect the high potential power supply line to two output terminals are turned ON, so as to bring the potential of each of the two output terminals to a logic level (the “H” level or the “L” level), thereby preventing a through current from flowing from the high potential power supply line to the low potential power supply line. Therefore, a high-speed and high-precision current comparison is made while reducing the through current during a reset mode.
    • 在电流比较型锁存器中,在时钟信号为“L”电平的当前比较型锁存器的复位模式期间,沿着从高电位电源线延伸到低电位电流的电流路径设置的晶体管 将高电位电源线连接到两个输出端子的晶体管导通,使两个输出端子的电位达到逻辑电平(“H”电平或“L” “电平”),从而防止贯通电流从高电位电源线流向低电位电源线。 因此,在复位模式期间,在减小通电电流的同时进行高速高精度电流比较。
    • 7. 发明申请
    • OPTICAL TRANSMISSION CIRCUIT
    • 光传输电路
    • US20090135866A1
    • 2009-05-28
    • US12093076
    • 2006-09-13
    • Kazuko NishimuraHiroshi Kimura
    • Kazuko NishimuraHiroshi Kimura
    • H01S3/04
    • H01S5/042H01S5/0612H01S5/068H01S5/183H03F3/08H04B10/504
    • An optical transmission circuit includes a light emitting device (10) having different temperature characteristics at low temperature and high temperature (e.g., a VCSEL (Vertical Cavity Surface Emitting Laser), differential switch transistors (M1, M2) for driving the light emitting device (10), the differential switch transistors having sources connected to each other and drains connected to the light emitting device (10) and a power supply, respectively, a bias current source (11) for causing a bias current to flow, a modulated current source (12) for causing a modulated current to flow, and a temperature compensation current source (20) for controlling currents of the bias current source (11) and the modulated current source (12) so as to compensate for both temperature characteristics at low temperature and temperature characteristics at high temperature of the light emitting device (10).
    • 光传输电路包括在低温和高温下具有不同温度特性的发光器件(例如,VCSEL(垂直腔表面发射激光器)),用于驱动发光器件的差分开关晶体管(M1,M2) 10),差分开关晶体管具有彼此连接的源极和连接到发光器件(10)的漏极和电源,分别用于使偏置电流流动的偏置电流源(11),调制电流源 (12),用于使调制电流流动;以及温度补偿电流源(20),用于控制偏置电流源(11)和调制电流源(12)的电流,以便补偿低温下的两个温度特性 和发光装置(10)的高温下的温度特性。
    • 8. 发明授权
    • Solid-state imaging device including A/D converting circuit with power-down controller
    • 固态成像装置包括具有掉电控制器的A / D转换电路
    • US08035066B2
    • 2011-10-11
    • US12212328
    • 2008-09-17
    • Yutaka AbeKazuko NishimuraHiroshi Kimura
    • Yutaka AbeKazuko NishimuraHiroshi Kimura
    • H01L27/00
    • H04N5/378H04N5/23241H04N5/3698
    • A solid-state imaging device includes pixels, arranged in a matrix, each of which converts light into a signal voltage. The solid-state imaging device also includes column signal lines, each of which is provided for corresponding one of columns, so that the signal voltage is provided to corresponding one of the column signal lines. Additionally, the solid-state imaging device includes AD converting units, each of which is provided for the corresponding one of the column signal lines, and is configured to convert the signal voltage into a digital signal. Each of the AD converting units includes a comparing unit generating an output signal indicating a greater voltage of the signal voltage and a reference voltage, and a counting unit counting a count value until logic of the output signal is inverted The solid-state imaging device further includes a suspending unit suspending power supply to the comparing units after the logic of the output signals is inverted.
    • 固态成像装置包括排列成矩阵的像素,每个像素将光转换成信号电压。 固态成像装置还包括列信号线,其中每一列被提供给相应的一列,使得信号电压被提供给相应的列信号线。 此外,固态成像装置包括AD转换单元,其各自被设置用于对应的一个列信号线,并且被配置为将信号电压转换为数字信号。 AD转换单元包括:比较单元,生成表示信号电压和参考电压的较大电压的输出信号;计数单元,计数输出信号的逻辑反转前的计数值。固态成像装置进一步 包括在输出信号的逻辑反转之后将暂停电源暂停到比较单元的电源。
    • 9. 发明授权
    • Optical transmission circuit
    • 光传输电路
    • US08023541B2
    • 2011-09-20
    • US12093076
    • 2006-09-13
    • Kazuko NishimuraHiroshi Kimura
    • Kazuko NishimuraHiroshi Kimura
    • H01S3/00H01S3/04
    • H01S5/042H01S5/0612H01S5/068H01S5/183H03F3/08H04B10/504
    • An optical transmission circuit includes a light emitting device (10) having different temperature characteristics at low temperature and high temperature (e.g., a VCSEL (Vertical Cavity Surface Emitting Laser), differential switch transistors (M1, M2) for driving the light emitting device (10), the differential switch transistors having sources connected to each other and drains connected to the light emitting device (10) and a power supply, respectively, a bias current source (11) for causing a bias current to flow, a modulated current source (12) for causing a modulated current to flow, and a temperature compensation current source (20) for controlling currents of the bias current source (11) and the modulated current source (12) so as to compensate for both temperature characteristics at low temperature and temperature characteristics at high temperature of the light emitting device (10).
    • 光传输电路包括在低温和高温下具有不同温度特性的发光器件(例如,VCSEL(垂直腔表面发射激光器)),用于驱动发光器件的差分开关晶体管(M1,M2) 10),差分开关晶体管具有彼此连接的源极和连接到发光器件(10)的漏极和电源,分别用于使偏置电流流动的偏置电流源(11),调制电流源 (12),用于使调制电流流动;以及温度补偿电流源(20),用于控制偏置电流源(11)和调制电流源(12)的电流,以便补偿低温下的两个温度特性 和发光装置(10)的高温下的温度特性。
    • 10. 发明授权
    • PLL circuit having a phase offset detecting phase comparator
    • PLL电路具有相位偏移检测相位比较器
    • US06542038B2
    • 2003-04-01
    • US09986288
    • 2001-11-08
    • Kazuko NishimuraToru Iwata
    • Kazuko NishimuraToru Iwata
    • H03L700
    • H03L7/087H03L7/081H03L7/0891H03L7/18
    • A phase-offset detecting phase comparator for comparing a reference signal and an auxiliary comparison signal which is a frequency-divided VCO output in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the auxiliary comparison signal by the first delay control signal to produce a comparison signal; a second delay element for adding delay to the VCO output by the second delay control signal to produce a PLL output; and a dummy frequency divider for adding delay corresponding to a frequency divider to the PLL output are provided.
    • 相位偏移检测相位比较器,用于比较基准信号和辅助比较信号,所述辅助比较信号是相位相位的分频VCO输出以检测相位偏移,并产生对应于相位偏移的第一和第二延迟控制信号; 第一延迟元件,用于通过第一延迟控制信号将延迟添加到辅助比较信号,以产生比较信号; 第二延迟元件,用于通过第二延迟控制信号向VCO输出添加延迟以产生PLL输出; 并且提供用于将对应于分频器的延迟添加到PLL输出的虚拟分频器。