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    • 1. 发明授权
    • Semiconductor device including resonance circuit
    • 包括谐振电路的半导体装置
    • US07923796B2
    • 2011-04-12
    • US11440030
    • 2006-05-25
    • Yutaka ShionoiriTomoaki AtsumiHiroki Inoue
    • Yutaka ShionoiriTomoaki AtsumiHiroki Inoue
    • H01L27/14G08B13/14
    • G06K19/07749G06K19/0723
    • It is an object of the present invention to provide a semiconductor device in which an arrangement area of capacitance can be reduced and resonance frequency can be easily adjusted. The semiconductor device includes an antenna and a resonance circuit including a capacitor connected to the antenna in parallel where the capacitor is formed by connecting x pieces of first capacitor (x is an arbitrary natural number), y pieces of second capacitor (y is an arbitrary natural number), and z pieces of third capacitor (z is an arbitrary natural number) in parallel; and the first capacitor, the second capacitor, and the third capacitor have different capacitance values from each other. It is preferable that each of the first capacitor, the second capacitor, and the third capacitor be a MIS capacitor. Further, at least one of the first capacitor, the second capacitor, and the third capacitor is preferably formed by connecting a plurality of capacitors in parallel.
    • 本发明的目的是提供一种半导体器件,其中可以减小电容的布置面积并且可以容易地调节谐振频率。 半导体器件包括天线和谐振电路,其包括并联连接到天线的电容器,其中通过连接x个第一电容器(x是任意自然数)形成电容器,y个第二电容器(y是任意的) 自然数)和z个第三电容器(z是任意自然数); 并且第一电容器,第二电容器和第三电容器具有彼此不同的电容值。 优选地,第一电容器,第二电容器和第三电容器中的每一个都是MIS电容器。 此外,优选通过并联连接多个电容器来形成第一电容器,第二电容器和第三电容器中的至少一个。
    • 2. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060267771A1
    • 2006-11-30
    • US11440030
    • 2006-05-25
    • Yutaka ShionoiriTomoaki AtsumiHiroki Inoue
    • Yutaka ShionoiriTomoaki AtsumiHiroki Inoue
    • G08B13/14
    • G06K19/07749G06K19/0723
    • It is an object of the present invention to provide a semiconductor device in which an arrangement area of capacitance can be reduced and resonance frequency can be easily adjusted. The semiconductor device includes an antenna and a resonance circuit including a capacitor connected to the antenna in parallel where the capacitor is formed by connecting x pieces of first capacitor (x is an arbitrary natural number), y pieces of second capacitor (y is an arbitrary natural number), and z pieces of third capacitor (z is an arbitrary natural number) in parallel; and the first capacitor, the second capacitor, and the third capacitor have different capacitance values from each other. It is preferable that each of the first capacitor, the second capacitor, and the third capacitor be a MIS capacitor. Further, at least one of the first capacitor, the second capacitor, and the third capacitor is preferably formed by connecting a plurality of capacitors in parallel.
    • 本发明的目的是提供一种半导体器件,其中可以减小电容的布置面积并且可以容易地调节谐振频率。 半导体器件包括天线和谐振电路,其包括并联连接到天线的电容器,其中通过连接x个第一电容器(x是任意自然数)形成电容器,y个第二电容器(y是任意的) 自然数)和z个第三电容器(z是任意自然数); 并且第一电容器,第二电容器和第三电容器具有彼此不同的电容值。 优选地,第一电容器,第二电容器和第三电容器中的每一个都是MIS电容器。 此外,优选通过并联连接多个电容器来形成第一电容器,第二电容器和第三电容器中的至少一个。
    • 5. 发明授权
    • Memory and driving method of the same
    • 内存和驱动方法相同
    • US07352604B2
    • 2008-04-01
    • US11607053
    • 2006-12-01
    • Yutaka ShionoiriTomoaki AtsumiKiyoshi Kato
    • Yutaka ShionoiriTomoaki AtsumiKiyoshi Kato
    • G11C17/00
    • G11C7/1096G11C7/1078G11C7/12G11C11/4094G11C17/12
    • According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
    • 根据本发明,通过减少元件的数量来减小安装面积并提高产量,并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元,其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件,列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线,而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中,源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。
    • 8. 发明申请
    • Semiconductor device and wireless communication system using the same
    • 半导体器件和使用其的无线通信系统
    • US20090079572A1
    • 2009-03-26
    • US11919497
    • 2006-05-17
    • Tomoaki AtsumiYutaka ShionoiriHidetomo Kobayashi
    • Tomoaki AtsumiYutaka ShionoiriHidetomo Kobayashi
    • G08B13/22
    • G06K19/07749G06K19/0708
    • Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.
    • 可以有效地执行半导体器件的初始化,其通过无线通信发送和接收数据。 半导体器件包括天线,电源电路,使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端,并接收无线信号(调制载波)。 电源电路包括第一端子和第二端子,并且通过使用接收的无线信号(调制载波)在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式,半导体器件和无线通信系统可以准确地发送和接收数据。
    • 9. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07319633B2
    • 2008-01-15
    • US11013426
    • 2004-12-17
    • Yutaka ShionoiriTomoaki Atsumi
    • Yutaka ShionoiriTomoaki Atsumi
    • G11C8/00
    • G11C16/08
    • A semiconductor device in which a current consumption when a word line being selected is suppressed and accurate data reading is carried out. The semiconductor device of a semiconductor device of the invention comprises a data storage means and a power source control means. The data storage means has a plurality of memory cells. The power source control means has at least one power source line and a plurality of switches. In addition, the invention further comprises an address selection means having a selector circuit including a plurality of switches and an output bus, a first decoder circuit for selecting the switch in the selector circuit, and a second decoder circuit.
    • 当抑制所选择的字线时的电流消耗并且执行准确的数据读取的半导体器件。 本发明的半导体器件的半导体器件包括数据存储装置和电源控制装置。 数据存储装置具有多个存储单元。 电源控制装置具有至少一个电源线和多个开关。 另外,本发明还包括地址选择装置,具有包括多个开关和输出总线的选择器电路,用于选择选择器电路中的开关的第一解码器电路和第二解码器电路。