专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4769275A Coated cloth 失效
标题翻译：涂布
公开(公告)号：US4769275A
公开(公告)日：1988-09-06
申请号：US15631
申请日：1987-02-17
申请人： Yutaka Inagaki , Susumu Yamada , Saburo Fukushima
发明人： Yutaka Inagaki , Susumu Yamada , Saburo Fukushima
IPC分类号： D06M11/00 , D06M11/44 , D06M11/45 , D06M11/79 , D06M11/83 , D06M15/00 , D06M23/08 , D06N7/00 , B32B5/16
CPC分类号： D06N7/00 , Y10T442/2631 , Y10T442/273
摘要： A coated cloth, wherein a blend containing from 50 to 400 parts by weight of a hydroxide and more than 3 parts by weight of powdery fibers based on 100 parts by weight of a base polymer not containing halogen elements is coated on a cloth. The coated cloth is excellent in abrasion resistance and flame retardance, as well as releasing less smoke.
摘要翻译：一种涂布布，其中包含50-400重量份氢氧化物和大于3重量份基于100重量份不含卤素元素的基础聚合物的粉末纤维的共混物涂布在布上。涂布布的耐磨性和阻燃性优异，并且释放较少的烟雾。

2. 发明申请

US20110074473A1 RESET CIRCUIT 有权
标题翻译：复位电路
公开(公告)号：US20110074473A1
公开(公告)日：2011-03-31
申请号：US12893755
申请日：2010-09-29
申请人： Susumu Yamada
发明人： Susumu Yamada
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , G06F1/24
摘要： In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.
摘要翻译：在一些实施例中，配备有备用电力电容器的电子电路的复位电路包括布置成检测备用电容器的预定第一电压的第一检测器，布置成检测备用电容器的预定第二电压的第二检测器，第二检测器电压低于第一电压，以及控制器，其布置成基于第一检测器和第二检测器的检测结果来控制复位请求信号的输出。控制器被配置为当第二检测器检测到第二检测器之后第一检测器检测到第一电压时，输出复位请求信号。

3. 发明授权

US07227333B2 Battery, device and charger 有权
标题翻译：电池，设备和充电器
公开(公告)号：US07227333B2
公开(公告)日：2007-06-05
申请号：US10696666
申请日：2003-10-29
申请人： Susumu Yamada , Tsunehiko Yatsu
发明人： Susumu Yamada , Tsunehiko Yatsu
IPC分类号： H02J7/00
CPC分类号： H01M10/48 , H01M10/46
摘要： A battery comprising a storage section for storing battery management information transmitted/received to/from outside through a communicator; wherein, the battery management information is at least either available device information on a device which can use the battery or chargeable charger information on a charger which can charge the battery.
摘要翻译：一种电池，包括：存储部，用于通过通信器存储从外部发送/接收的电池管理信息; 其中，所述电池管理信息至少是可以在可以对可对电池充电的充电器上使用电池或可充电充电器信息的装置上的可用装置信息。

4. 发明申请

US20050060523A1 Microcomputer and evaluation device, evaluation method thereof 有权
标题翻译：微电脑及评估装置及其评估方法
公开(公告)号：US20050060523A1
公开(公告)日：2005-03-17
申请号：US10741742
申请日：2003-12-18
申请人： Susumu Yamada , Tadao Nakamura , Susumu Kubota
发明人： Susumu Yamada , Tadao Nakamura , Susumu Kubota
IPC分类号： G06F11/28 , G06F7/38 , G06F9/00 , G06F9/32 , G06F9/44 , G06F11/22 , G06F15/00 , G06F15/78
CPC分类号： G06F11/362
摘要： Address data in an address counter is evaluated correctly. A microcomputer which outputs address data to an external device for evaluating the address data comprising an address counter specifying an address in a program memory, an address data output section which outputs, to the external device, discrimination data for discriminating whether or not the address data in the address counter is one which is branched in order for the external device to store only branched address data, the discrimination data being outputted together with the address data.
摘要翻译：地址计数器中的地址数据被正确评估。向外部设备输出地址数据的微型计算机，用于评估地址数据，该地址数据包括指定程序存储器中的地址的地址计数器，输出到外部设备的地址数据输出部分，用于鉴别地址数据在地址计数器中，为了使外部设备仅存储分支的地址数据而被分支的地址计数器，所述鉴别数据与地址数据一起输出。

5. 发明授权

US06462804B1 Display apparatus and its cooling method 失效
标题翻译：显示装置及其冷却方式
公开(公告)号：US06462804B1
公开(公告)日：2002-10-08
申请号：US09283184
申请日：1999-04-01
申请人： Susumu Yamada , Hiroshi Takatsuka , Hiroyuki Ono
发明人： Susumu Yamada , Hiroshi Takatsuka , Hiroyuki Ono
IPC分类号： G02F11333
CPC分类号： G03B21/16
摘要： A display apparatus and its cooling method in which the optical assemblies can be prevented from being smudged by dust entered into the apparatus so that an excellent image can be obtained and the apparatus can be cooled sufficiently with the apparatus including a housing having a screen on its front surface and a closed structure, an optical block having a closed structure and coupled with the housing in a closed fashion allowing air to circulate between the housing and the optical block. Further, the display apparatus includes a light source, a first cooling device for cooling the light source and a second cooling device for cooling the optical block. At least the optical block is arranged to have a closed structure and is cooled by air circulation.
摘要翻译：一种显示装置及其冷却方法，其中可以防止光学组件被进入设备的灰尘弄脏，从而可以获得优异的图像，并且该设备可以被充分地冷却，该设备包括具有屏幕的壳体前表面和封闭结构，光学块具有封闭的结构，并以闭合的方式与壳体联接，使得空气在壳体和光学块之间循环。此外，显示装置包括光源，用于冷却光源的第一冷却装置和用于冷却光学块的第二冷却装置。至少光学块被布置成具有封闭的结构并且被空气循环冷却。

6. 发明授权

US06450522B1 Transporting vehicle 有权
标题翻译：运输车辆
公开(公告)号：US06450522B1
公开(公告)日：2002-09-17
申请号：US09675625
申请日：2000-09-29
申请人： Susumu Yamada , Heinz-Bernd Langendorf
发明人： Susumu Yamada , Heinz-Bernd Langendorf
IPC分类号： B62D2114
CPC分类号： B60P1/025 , B62D53/045 , B62D53/062
摘要： In a transporting vehicle provided with a trailer hauled by a tractor, the trailer is constructed by a first trailer unit connectable with the tractor and a second trailer unit detachably connectable with the first trailer unit. At mutually opposed connecting sections of the first and second trailer units is provided a connecting mechanism for integrally connecting the first and second trailer units with the rear end of the first trailer unit held in contact with the front end of the second trailer unit. The transporting vehicle can transport cargoes on roads other than main roads while being allowed to have a relatively simple construction and an improved loading capacity.
摘要翻译：在设置有由拖拉机牵引的拖车的运输车辆中，拖车由可拖拉机连接的第一拖车单元和可拆卸地与第一拖车单元连接的第二拖车单元构成。在第一拖车单元和第二拖车单元的相互相对的连接部分设置有连接机构，用于将第一和第二拖车单元一体地连接，并且第一拖车单元的后端与第二拖车单元的前端保持接触。运输车辆可以在主要道路以外的道路上运输货物，同时允许其具有相对简单的结构和改进的承载能力。

7. 发明授权

US06400718B1 Cell switching device capable of effecting hit-less switching between an active system and a standby system 失效
标题翻译：小区切换设备能够在主动系统和备用系统之间实现无冲突切换
公开(公告)号：US06400718B1
公开(公告)日：2002-06-04
申请号：US09311865
申请日：1999-05-14
申请人： Susumu Yamada , Kazuho Kawaguchi , Akiyoshi Shimizu
发明人： Susumu Yamada , Kazuho Kawaguchi , Akiyoshi Shimizu
IPC分类号： H04L122
CPC分类号： H04L49/30 , H04L1/22 , H04L49/254 , H04L49/503 , H04L49/55
摘要： A hit-less cell switching device capable of switching ATM (Asynchronous Transfer Mode) cells between a system ZERO and a system ONE is disclosed. The system ZERO includes a first cell switch, a first input cell gate, a first output cell gate, and a first shaper. Likewise, the system ONE includes a second cell switch, a second input cell gate, a second output cell gate, and a second shaper. First, a controller opens the first and second input cell gates and first output cell gate, closes the second output cell gate, and puts the first and second cell switches and first and second shapers in a fully switched condition, thereby initializing the switching device. Subsequently, the controller closes the second input cell gate, evacuates queue buffers included in the second cell switch and second shaper, and opens the second output gate. After putting the two cell switches and two shapers in an in-switching state, the controller closes the first input cell gate and opens the second input cell gate simultaneously. When the first cell switch and first shaper are evacuated and the arrival of cells ends, the controller causes the second cell switch and second shaper to read cells out of their queue buffers, respectively. On confirming the end of switching of the first cell switch and first shaper, the controller closes the first output cell gate and opens the first input cell gate, thereby completing switching from the system ZERO to the system ONE.
摘要翻译：公开了一种能够在系统零和系统ONE之间切换ATM（异步传输模式）小区的无点击小区切换设备。系统ZERO包括第一单元开关，第一输入单元门，第一输出单元门和第一整形器。类似地，系统ONE包括第二单元开关，第二输入单元门，第二输出单元门和第二整形器。首先，控制器打开第一和第二输入单元门和第一输出单元门，关闭第二输出单元门，并将第一和第二单元开关以及第一和第二成形器置于完全切换状态，从而初始化开关器件。随后，控制器关闭第二输入单元门，排出包括在第二单元开关和第二整形器中的排队缓冲器，并打开第二输出门。在将两个单元开关和两个成形器置于开关状态之后，控制器关闭第一输入单元门并同时打开第二输入单元门。当第一单元开关和第一整形器被排空并且单元的到达结束时，控制器使第二单元开关和第二整形器分别从其排队缓冲器中读出单元。在确认第一单元开关和第一整形器的切换结束时，控制器关闭第一输出单元门并打开第一输入单元门，从而完成从系统零切换到系统ONE。

8. 发明授权

US5950222A Microcomputer using a non-volatile memory 失效
标题翻译：微机使用非易失性存储器
公开(公告)号：US5950222A
公开(公告)日：1999-09-07
申请号：US811572
申请日：1997-03-05
申请人： Susumu Yamada , Toru Watanabe , Nobuhiro Arai , Toshikazu Abe
发明人： Susumu Yamada , Toru Watanabe , Nobuhiro Arai , Toshikazu Abe
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246
摘要： An EEPROM (1) is set to write mode when a program command to commence rewriting of data in region B in the EEPROM (1) is read out from region A. A CPU (2) then writes data specified by a latch (6) at an address in region B specified by a latch (4). In compliance with an inhibit signal INH, the CPU (2) now disregards the effects of the undefined output from the EEPROM (1) terminal DOUT.
摘要翻译：当从区域A读出在EEPROM（1）中的区域B中开始重写数据的程序命令时，将EEPROM（1）设置为写入模式。然后，CPU（2）写入由锁存器（6）指定的数据，在由闩锁（4）指定的区域B中的地址处。根据禁止信号INH，CPU（2）现在忽略来自EEPROM（1）端子DOUT的未定义输出的影响。

9. 发明授权

US5500825A Parallel data outputting storage circuit 失效
标题翻译：并行数据输出存储电路
公开(公告)号：US5500825A
公开(公告)日：1996-03-19
申请号：US268165
申请日：1994-06-28
申请人： Masato Onaya , Susumu Yamada
发明人： Masato Onaya , Susumu Yamada
IPC分类号： G06F12/06 , G11C7/16 , G11C8/04 , G11C8/12 , G11C7/00
CPC分类号： G11C8/12 , G11C7/16 , G11C8/04 , G11C2207/16
摘要： A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.
摘要翻译：可以容易地获得多个延迟时间数据。数据输入单元32将数据连续地写入存储器30.数据输出单元36以并行方式从存储器30中的六个区域a-f输出数据。选择单元SW1和SW2连续选择并输出从存储器30中的六个区域a-f读出的数据。要被读取的位置由选择单元SW1和SW2彼此移位，以从不同的存储器位置输出数据。因此，可以同时获得写入和读出操作之间的时间不同的多个数据（即不同的延迟时间）。

10. 发明授权

US08410841B2 Input/output circuit 失效
标题翻译：输入/输出电路
公开(公告)号：US08410841B2
公开(公告)日：2013-04-02
申请号：US13238664
申请日：2011-09-21
申请人： Susumu Yamada
发明人： Susumu Yamada
IPC分类号： H03K17/687 , H03K17/00
CPC分类号： G06F13/4072 , G06F1/3253 , Y02D10/151
摘要： In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.
摘要翻译：在一些实施例中，输入/输出（I / O）电路经由设置在通信线路上的耦合电容发送和接收高电平信号和低电平信号。所述I / O电路包括：接收部，包括被配置为检测所述信号之一的第一检测电路;以及被配置为检测所述另一信号的第二检测电路;发送部，包括三值输出电路，被配置为输出以下信号之一：高电平信号，低电平信号和高阻抗信号，以及被配置为控制接收部分和发送部分的控制电路。控制电路根据接收状态下的第一检测电路和第二检测电路的检测结果来判断输入信号的电平，并且控制三值输出电路的输出值处于发送状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式