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1. 发明授权

US5777371A High-breakdown-voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5777371A
公开(公告)日：1998-07-07
申请号：US716863
申请日：1996-09-20
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hideyuki Funaki
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hideyuki Funaki
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/1095 , H01L29/7801 , H01L29/7824 , H01L29/42368
摘要： A high-breakdown-voltage semiconductor device includes a high-resistance semiconductor layer, a drift layer of the first conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a drain layer formed in the surface of the drift layer of the first conductivity type, base layers of the second conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a plurality of island-shaped source layers of the first conductivity type formed in the surfaces of the base layers of the second conductivity type, a gate electrode formed on the base layers of the second conductivity type between the source layers of the first conductivity type and the drift layer of the first conductivity type and between adjacent source layers of the first conductivity type via a gate insulating film, a drain electrode which contacts the drain layer, and source electrodes which contact both the source layers of the first conductivity type and the base layers of the second conductivity type.
摘要翻译：高耐压半导体器件包括高电阻半导体层，选择性地形成在高电阻半导体层的表面中的第一导电类型的漂移层，形成在所述高电阻半导体层的漂移层的表面中的漏极层第一导电类型，选择性地形成在高电阻半导体层的表面中的第二导电类型的基极层，形成在第二导电类型的基极层的表面中的多个第一导电类型的岛状源极层形成在第一导电类型的源极层和第一导电类型的漂移层之间的第二导电类型的基极层上的栅极电极和经由栅极绝缘膜的第一导电类型的相邻源极层之间，与漏极层接触的电极以及接触第一导电类型的源极层的源电极第二导电类型的基层。

2. 发明授权

US5985708A Method of manufacturing vertical power device 失效
标题翻译：垂直功率器件的制造方法
公开(公告)号：US5985708A
公开(公告)日：1999-11-16
申请号：US816596
申请日：1997-03-13
申请人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L27/12 , H01L29/73 , H01L29/739 , H01L29/786 , H01L21/8249
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/7317 , H01L29/7394 , H01L29/78612 , H01L29/78624 , H01L29/78639 , H01L29/78645 , H01L29/78687
摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
摘要翻译：一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层，所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极，以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置不同于第二导电型基底层，和多晶半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

3. 发明授权

US5635736A MOS gate type semiconductor device 失效
标题翻译： MOS栅型半导体器件
公开(公告)号：US5635736A
公开(公告)日：1997-06-03
申请号：US527729
申请日：1995-09-13
申请人： Hideyuki Funaki , Yoshihiro Yamaguchi
发明人： Hideyuki Funaki , Yoshihiro Yamaguchi
IPC分类号： H01L23/482 , H01L27/08 , H01L29/06 , H01L29/417 , H01L29/78 , H01L29/786 , H01L27/10
CPC分类号： H01L27/0802 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/41758 , H01L29/7835 , H01L2924/0002
摘要： A MOS gate type semiconductor device, comprising an upper source wiring consisting of a plurality of upper source electrodes, an upper drain wiring provided on a semiconductor substrate and consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes, lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes, and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes electrode such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape.
摘要翻译：一种MOS栅型半导体器件，包括由多个上源电极组成的上源极布线，设置在半导体衬底上的上漏极布线，并且由形成为梳状布置的多个上漏电极组成，上部漏电极与上部源电极接合，设置在相邻成对的上部源电极和上部漏电极的下部的下部源电极，使得下部源电极层叠在上部源电极和上部漏极电极和下漏电极，其设置在相邻成对的上源电极和上漏电极电极的下部，使得下漏电极层叠在上源电极和上漏电极的下方，其中下源电极连接到上源电极和源区，a d被配置成波形形状，下部漏极连接到上部漏电极和漏极区域，并且被配置为形成波浪形状。

4. 发明授权

US5438220A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5438220A
公开(公告)日：1995-08-01
申请号：US085056
申请日：1993-07-02
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/78603 , H01L2924/0002
摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.
摘要翻译：高耐压半导体器件包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。第一杂质区由扩散层形成。扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

5. 发明授权

US5981983A High voltage semiconductor device 失效
标题翻译：高压半导体器件
公开(公告)号：US5981983A
公开(公告)日：1999-11-09
申请号：US933135
申请日：1997-09-18
申请人： Hideyuki Funaki , Yoshihiro Yamaguchi
发明人： Hideyuki Funaki , Yoshihiro Yamaguchi
IPC分类号： H01L29/417 , H01L29/739 , H01L29/68
CPC分类号： H01L29/41758 , H01L29/7394
摘要： A semiconductor device includes a substrate, an insulating layer formed on the substrate, a base layer of a first conductivity type formed on the insulating layer, a drain layer of a second conductivity type selectively formed above the surface of the base layer of the first conductivity type, a drain electrode formed on and connected to the drain layer of the second conductivity type, a base layer of the second conductivity type selectively formed on the base layer of the first conductivity type, a source layer of the first conductivity type isolated from the base layer of the first conductivity type and selectively formed in the surface area of the base layer of the second conductivity type, a source electrode formed on and connected to the source layer of the first conductivity type and the base layer of the second conductivity type, and a gate electrode formed above a portion of the base layer of the second conductivity type which lies between the source layer of the first conductivity type and the base layer of the first conductivity type with a gate insulating film disposed therebetween.
摘要翻译：半导体器件包括基板，形成在基板上的绝缘层，形成在绝缘层上的第一导电类型的基极层，第二导电类型的漏极层，选择性地形成在第一导电性的基底层表面上方形成在第二导电类型的漏极层上并连接到第二导电类型的漏极层的漏电极，选择性地形成在第一导电类型的基极层上的第二导电类型的基极层，与第一导电类型的第一导电类型隔离的源极层第一导电类型的基底层，并且选择性地形成在第二导电类型的基底层的表面区域中，形成在第一导电类型的源极层和第二导电类型的基极层上并连接到第二导电类型的源极层的源电极，以及形成在位于第一导电体的源极层之间的第二导电类型的基底层的一部分上方的栅电极 vity型和第一导电类型的基底层，其间设置有栅极绝缘膜。

6. 发明授权

US5640040A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5640040A
公开(公告)日：1997-06-17
申请号：US481097
申请日：1995-06-07
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura , Hideyuki Funaki
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L23/58
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/78603 , H01L2924/0002
摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.
摘要翻译：一种高耐压电压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上并由第一导电类型的高电阻半导体形成的有源层，第一导电类型的第一杂质区形成在有源层中的第二杂质区和形成在有源层中并与第一杂质区隔开预定距离的第二导电类型的第二杂质区。第一杂质区由扩散层形成。扩散层彼此叠加并且扩散深度或扩散窗宽度不同，或两者均不同。

7. 发明授权

US5592014A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5592014A
公开(公告)日：1997-01-07
申请号：US484864
申请日：1995-06-07
申请人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura
发明人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai , Yoshihiro Yamaguchi , Ichiro Omura
IPC分类号： H01L21/336 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L23/58
CPC分类号： H01L29/404 , H01L21/76264 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L2924/0002
摘要： A high breakdown voltage semiconductor apparatus comprises a substrate having an insulating layer formed thereon, a high resistance semiconductor layer of a first conductivity type formed on said insulating layer, a base region of the first conductivity type formed selectively in a surface region of the high resistance semiconductor layer, a drift region of a second conductivity type formed selectively in the surface region of the high resistance semiconductor layer so as not to reach the insulating layer, a source region of the second conductivity type formed in the base region, a drain region formed in the drift region, a gate electrode formed on a region between the source region and the drift region, with a gate insulating film interposed between the gate electrode and the region between the source region and the drift region, a source electrode provided in contact with the base region and the source region, a drain electrode provided in contact with the drain region. The dosage of impurities in the high resistance semiconductor layer is 2.times.10.sup.12 cm.sup.-2 to 3.times.10.sup.12 cm.sup.-2 and the dosage of impurities in the drift layer is 1.times.10.sup.12 cm.sup.-2 to 2.times.10.sup.12 cm.sup.-2.
摘要翻译：一种高耐压电压半导体装置，包括：在其上形成有绝缘层的基板，形成在所述绝缘层上的第一导电类型的高电阻半导体层，所述第一导电类型的基极区选择性地形成在所述高电阻的表面区域中半导体层，选择性地形成在高电阻半导体层的表面区域中以便不到达绝缘层的第二导电类型的漂移区域，形成在基极区域中的第二导电类型的源极区域，形成的漏极区域在漂移区域中，形成在源极区域和漂移区域之间的区域上的栅电极，栅极绝缘膜插入在栅极电极和源极区域与漂移区域之间的区域中，源极电极与所述基极区域和所述源极区域，设置成与所述漏极区域接触的漏极电极。高电阻半导体层中的杂质用量为2×10 12 cm -2至3×10 12 cm -2，漂移层中的杂质用量为1×10 12 cm -2至2×10 12 cm -2。

8. 发明授权

US07872308B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07872308B2
公开(公告)日：2011-01-18
申请号：US12332260
申请日：2008-12-10
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
摘要翻译：半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极，并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层，设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。第五半导体层的最上部与第三半导体层接触，第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高，位于第二半导体层中，第一半导体层，第五半导体层从最上部到最下部较窄。

9. 发明授权

US07485921B2 Trench gate type MOS transistor semiconductor device 失效
标题翻译：沟槽型MOS晶体管半导体器件
公开(公告)号：US07485921B2
公开(公告)日：2009-02-03
申请号：US11674337
申请日：2007-02-13
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译：该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。端接层形成为具有大于基底层的结深度的结深度。

10. 发明授权

US07479678B2 Semiconductor element and method of manufacturing the same 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US07479678B2
公开(公告)日：2009-01-20
申请号：US11485284
申请日：2006-07-13
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.
摘要翻译：提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

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