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1. 发明授权

US06298473B1 Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device 失效
标题翻译：用于抑制图案失真以校正半导体器件中的图案数据的装置和方法
公开(公告)号：US06298473B1
公开(公告)日：2001-10-02
申请号：US09204281
申请日：1998-12-03
申请人： Yusaku Ono , Koichi Moriizumi
发明人： Yusaku Ono , Koichi Moriizumi
IPC分类号： G06F760
CPC分类号： G03F7/70441 , G03F1/36
摘要： A correction target edge extracting part of a layout pattern data correction apparatus extracts a correction target edge from circuit layout patterns. A density calculation region setting part of the apparatus sets density calculation regions around the center of the correction target edge. An area density calculating part calculates an area density of design patterns within the density calculation regions. Given the area density thus calculated, a correction pattern size calculating part calculates the size of a correction pattern to be superposed on the correction target edge. In accordance with the calculated size, a correction pattern generating part generates the correction pattern. A graphic calculating part adds up the correction pattern and design layout patterns to generate corrected layout patterns.
摘要翻译：布局图案数据校正装置的校正目标边缘提取部分从电路布局图案中提取校正目标边缘。设备的密度计算区域设置部分设置校正目标边缘的中心周围的密度计算区域。区域密度计算部分计算密度计算区域内的设计图案的面积密度。给定如此计算的面积密度，校正图案尺寸计算部分计算要校正对象边缘上叠加的校正图案的尺寸。根据计算出的尺寸，校正图案生成部生成校正图案。图形计算部分将校正图案和设计布局图案相加，以生成校正的布局图案。

2. 发明申请

US20120091510A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEMICONDUCTOR MANUFACTURE, AND OPTICAL PROXIMITY CORRECTION METHOD 有权
标题翻译：半导体器件及其制造方法，半导体制造掩模和光学近似校正方法
公开(公告)号：US20120091510A1
公开(公告)日：2012-04-19
申请号：US13333577
申请日：2011-12-21
申请人： Hironobu TAOKA , Yusaku Ono
发明人： Hironobu TAOKA , Yusaku Ono
IPC分类号： H01L23/52 , H01L27/118
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

3. 发明授权

US08458627B2 Semiconductor device including logic circuit having areas of different optical proximity accuracy 有权
标题翻译：包括具有不同光学接近精度的区域的逻辑电路的半导体器件
公开(公告)号：US08458627B2
公开(公告)日：2013-06-04
申请号：US13333577
申请日：2011-12-21
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： G06F17/50 , H01L27/118 , H01L25/00 , H03K19/173
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

4. 发明授权

US06848096B2 Apparatus for correcting data of layout pattern 失效
标题翻译：用于校正布局图案数据的装置
公开(公告)号：US06848096B2
公开(公告)日：2005-01-25
申请号：US10424921
申请日：2003-04-29
申请人： Yusaku Ono
发明人： Yusaku Ono
IPC分类号： G03F1/36 , G03F1/68 , G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G06F17/5068
摘要： An apparatus for correcting layout pattern data composed of a computer system includes eight sections. The first section holds the layout pattern data. The second section holds correcting requirements. The third section extracts and divides correction target edges of the layout pattern. The fourth section sets a permissible correction range. The fifth section extracts insufficient process margin parts. The sixth section resets the permissible correction range. The seventh section performs correction by simulation. The eighth section holds finished correction layout pattern data. By simulation, the apparatus predicts finished layout patterns at high rate and high precision within the movable range of the correction target edges which can secure process margins.
摘要翻译：用于校正由计算机系统组成的布局图案数据的装置包括八个部分。第一部分保留布局模式数据。第二部分要求修正。第三部分提取和分割布局图案的校正目标边。第四部分设置允许的校正范围。第五部分提取过程余量部分不足。第六部分复位允许的校正范围。第七部分通过模拟进行校正。第八部分保存完成的校正布局图案数据。通过模拟，该装置在校正目标边缘的可移动范围内以高速率和高精度预测完成的布局图案，其可以确保处理余量。

5. 发明授权

US08103977B2 Semiconductor device and its manufacturing method, semiconductor manufacturing mask, and optical proximity processing method 有权
标题翻译：半导体器件及其制造方法，半导体制造掩模和光学邻近处理方法
公开(公告)号：US08103977B2
公开(公告)日：2012-01-24
申请号：US11919228
申请日：2006-04-25
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

6. 发明申请

US20090278569A1 Semiconductor Device and its Manufacturing Method, Semiconductor Manufacturing Mask, and Optical Proximity Processing Method 有权
标题翻译：半导体器件及其制造方法，半导体制造掩模和光学接近加工方法
公开(公告)号：US20090278569A1
公开(公告)日：2009-11-12
申请号：US11919228
申请日：2006-04-25
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： H01L25/04 , G03F1/00 , G03F7/20 , H01L21/66
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

7. 发明授权

US06536015B2 Apparatus and method of correcting layout pattern data, method of manufacturing semiconductor devices and recording medium 失效
公开(公告)号：US06536015B2
公开(公告)日：2003-03-18
申请号：US09810504
申请日：2001-03-19
申请人： Yusaku Ono
发明人： Yusaku Ono
IPC分类号： G06F1750
CPC分类号： G03F7/70433 , G03F7/70441
摘要： The invention provides an apparatus and a method of correcting layout pattern. The apparatus has a deletion region side extracting section for extracting sides of a region to be deleted having a predetermined shape such as protrusion, notch or step in a layout pattern of a circuit, a deletion-use pattern generator for generating a deletion-use pattern based on the extracted sides, and an operating section for executing a predetermined operation to the layout pattern with the deletion-use pattern so as to remove the region to be deleted from the original layout pattern.

8. 发明授权

US07844934B2 Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction 有权
标题翻译：用于设计能够减少光学邻近效应校正的处理时间的半导体集成电路布局的方法
公开(公告)号：US07844934B2
公开(公告)日：2010-11-30
申请号：US11486107
申请日：2006-07-14
申请人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
发明人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/5068
摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
摘要翻译：根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪层级单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

9. 发明申请

US20070124714A1 Method for designing semiconductor integrated circuit layout 有权
标题翻译：设计半导体集成电路布局的方法
公开(公告)号：US20070124714A1
公开(公告)日：2007-05-31
申请号：US11486107
申请日：2006-07-14
申请人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
发明人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068
摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
摘要翻译：根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪分层单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

10. 发明授权

US06687885B2 Correction of layout pattern data during semiconductor patterning process 失效
标题翻译：在半导体图案化过程中校正布局图案数据
公开(公告)号：US06687885B2
公开(公告)日：2004-02-03
申请号：US09793417
申请日：2001-02-27
申请人： Yusaku Ono
发明人： Yusaku Ono
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： A layout pattern data correction device includes: (a) edge extracting means for extracting a first target edge to be corrected from an original layout pattern of a circuit; (b) edge modifying region setting means for setting an edge modifying region in which the first target edge is modified with a predetermined point in the first target edge taken as a center; (c) edge modifying means for modifying the first target edge within the edge modifying region into a second target edge to be corrected; (d) corrected pattern forming means for forming a corrected pattern based on the second target edge; and (e) boolean operation means for performing a predetermined boolean operation based on both of the original layout pattern and the corrected pattern.
摘要翻译：布局图案数据校正装置包括：（a）边缘提取装置，用于从电路的原始布局图案提取要校正的第一目标边缘; （b）边缘修改区域设定装置，用于将第一目标边缘中的预定点以第一目标边缘进行修改的边缘修改区域设为中心; （c）边缘修改装置，用于将边缘修改区域内的第一目标边缘修改为待校正的第二目标边缘; （d）校正图案形成装置，用于基于第二目标边缘形成校正图案; 以及（e）布尔运算装置，用于基于原始布局图案和校正图案两者执行预定的布尔运算。

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