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1. 发明授权

US08103977B2 Semiconductor device and its manufacturing method, semiconductor manufacturing mask, and optical proximity processing method 有权
标题翻译：半导体器件及其制造方法，半导体制造掩模和光学邻近处理方法
公开(公告)号：US08103977B2
公开(公告)日：2012-01-24
申请号：US11919228
申请日：2006-04-25
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

2. 发明申请

US20090278569A1 Semiconductor Device and its Manufacturing Method, Semiconductor Manufacturing Mask, and Optical Proximity Processing Method 有权
标题翻译：半导体器件及其制造方法，半导体制造掩模和光学接近加工方法
公开(公告)号：US20090278569A1
公开(公告)日：2009-11-12
申请号：US11919228
申请日：2006-04-25
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： H01L25/04 , G03F1/00 , G03F7/20 , H01L21/66
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

3. 发明授权

US08458627B2 Semiconductor device including logic circuit having areas of different optical proximity accuracy 有权
标题翻译：包括具有不同光学接近精度的区域的逻辑电路的半导体器件
公开(公告)号：US08458627B2
公开(公告)日：2013-06-04
申请号：US13333577
申请日：2011-12-21
申请人： Hironobu Taoka , Yusaku Ono
发明人： Hironobu Taoka , Yusaku Ono
IPC分类号： G06F17/50 , H01L27/118 , H01L25/00 , H03K19/173
CPC分类号： H03K19/094 , E21B43/24 , E21B47/06 , E21B47/123 , H01L27/0203
摘要： An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
摘要翻译：本发明的目的是减少包括逻辑电路的半导体器件的处理时间和制造成本。为了实现上述目的，用于形成逻辑电路的区域（114）包括以预定精度进行光学邻近校正的第一区域（114b，170）和经受光学的第二区域（114a，180）精度低于所述预定精度的接近校正。特别地，第一区域（114b，170）包括用作晶体管的栅极互连线（172），第二区域（114a，180）包括不用作晶体管的虚拟布局图案（182）。

4. 发明授权

US06343370B1 Apparatus and process for pattern distortion detection for semiconductor process and semiconductor device manufactured by use of the apparatus or process 有权
标题翻译：用于通过使用该装置或工艺制造的半导体工艺和半导体器件的图案失真检测的装置和工艺
公开(公告)号：US06343370B1
公开(公告)日：2002-01-29
申请号：US09203582
申请日：1998-12-02
申请人： Hironobu Taoka , Koichi Moriizumi
发明人： Hironobu Taoka , Koichi Moriizumi
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70433 , G03F7/70441 , G03F7/705
摘要： A finished pattern that will be formed based on a design layout pattern in a semiconductor manufacturing process is predicted, and the outline of the predicted finished pattern is converted into a polygon. On the other hand, test reference patterns are formed based on the design layout pattern. A pattern distortion in the predicted finished pattern is detected by comparing the polygonized predicted finished pattern with the test referencepatterns. In converting the predicted finished pattern into a polygon, the number of apices of the polygon is reduced. Two kinds of test reference patterns are formed: an upper limit test reference pattern obtained by reducing the design layout pattern and defining an allowable upper limit and a lower limit test reference pattern obtained by enlarging the design layout pattern and defining an allowable lower limit.
摘要翻译：预测将在半导体制造工艺中基于设计布图图案形成的成品图案，并将预测的完成图案的轮廓转换为多边形。另一方面，基于设计布局图形形成测试参考图案。通过将多边形预测完成图案与测试参考图案进行比较来检测预测完成图案中的图案失真。在将预测的完成图案转换成多边形时，多边形的顶点的数量减少。形成两种测试参考图案：通过减小设计布局图案并定义通过扩大设计布局图案并定义允许下限而获得的允许上限和下限测试参考图案而获得的上限测试参考图案。

5. 发明授权

US5796408A Charged particle beam drawing data production apparatus and charged particle beam drawing system 失效
标题翻译：带电粒子束图数据生产装置和带电粒子束拉制系统
公开(公告)号：US5796408A
公开(公告)日：1998-08-18
申请号：US555074
申请日：1995-11-08
申请人： Kinya Kamiyama , Koichi Moriizumi , Makoto Kanno , Hironobu Taoka
发明人： Kinya Kamiyama , Koichi Moriizumi , Makoto Kanno , Hironobu Taoka
IPC分类号： H01L21/027 , H01J37/302 , G06F15/00
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J37/3026 , H01J2237/31776
摘要： A system for preventing deterioration of dimensional accuracy by reducing production of micro graphics at the time of production of drawing data to be input to a charged particle beam drawing apparatus. A CPU divides a design layout data into units of graphic data processing area (a step S1) and executes elimination of duplication and tone reversal processes in both X direction and Y direction (steps S2A, S2B) for the respective graphic data processing areas. Moreover, it performs, with reference to a micro graphic dimensional value, the graphic data processing result judging and selecting function in both the X direction and Y direction (a step S3) for the respective graphic data processing areas. Namely, the CPU judges as the micro graphic when the dimension of a basic graphic after the elimination of duplication and tone reversal processes is no larger than the micro graphic dimensional value, compares the two by determining the sum of such micro graphics, for example, in the X, Y directions and selects the graphic data submitted to the elimination of duplication and tone reversal process for the direction with smaller value. The CUP further performs prescribed processing (steps S4, S5) of this graphic data to complete the production of drawing data.
摘要翻译：一种用于通过在生产要输入到带电粒子束描绘装置的绘图数据时减少微图形的生成来防止尺寸精度的劣化的系统。 CPU将设计布局数据分割为图形数据处理区域（步骤S1），并执行各图形数据处理区域的X方向和Y方向上的复制和色调反转处理的消除（步骤S2A，S2B）。另外，在各图形数据处理区域的X方向和Y方向（步骤S3）中，参照微图形维度值执行图形数据处理结果判定选择功能。即，当消除复制和色调反转处理之后的基本图形的尺寸不大于微图形尺寸值时，CPU判断为微图形，通过确定这样的微图形的总和来比较两者，例如，在X，Y方向上选择提取的图形数据，以消除重复和色调反转过程的方向，具有较小的值。 CUP进一步执行该图形数据的规定处理（步骤S4，S5）以完成绘图数据的制作。

6. 发明授权

US08930857B2 Mask data verification apparatus, design layout verification apparatus, method thereof, and computer program thereof 有权
标题翻译：掩模数据验证装置，设计布局验证装置，方法及其计算机程序
公开(公告)号：US08930857B2
公开(公告)日：2015-01-06
申请号：US13491082
申请日：2012-06-07
申请人： Hironobu Taoka
发明人： Hironobu Taoka
IPC分类号： G06F17/50 , G03F1/36 , G03F1/70
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.
摘要翻译：掩模数据验证装置将设计布局与存储在现有型库中的设计布局图案进行比较，并提取发现与新型设计布局图案不相等或相似的设计布局图案。掩模数据验证装置参照存储在新型库中的新的设计布局图案，使用OPC / RET生成掩模数据，并执行后验证。掩模数据验证装置可以预先验证新的设计布局图案，缩短半导体器件制造周期，确保有效开发，并提高制造产量。

7. 发明授权

US06427225B1 Method and apparatus for verification of a circuit layout 失效
标题翻译：用于验证电路布局的方法和装置
公开(公告)号：US06427225B1
公开(公告)日：2002-07-30
申请号：US09239148
申请日：1999-01-28
申请人： Osamu Kitada , Terutoshi Yamasaki , Hironobu Taoka
发明人： Osamu Kitada , Terutoshi Yamasaki , Hironobu Taoka
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/36
摘要： A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.
摘要翻译：根据图案形状，包括尺寸精度的半导体集成电路布局图以高精度有效地验证。一种用于基于向量数据验证布图是否符合设计规则的布局验证方法，包括：参考矢量分类步骤，用于选择和分类参考矢量，所述参考矢量用作对应于侧面的矢量中的验证参考，验证对象矢量分类步骤，用于选择和分类对应于所述边的矢量中的待验证对象矢量;以及验证步骤，用于验证在要被验证的所述待验证矢量之间的距离，与参考矢量的方向对应。

8. 发明授权

US06271852B1 boundary processing of oblique overlapping graphics to achieve dimensionally accurate electron beam irradiation 失效
标题翻译：倾斜重叠图形的边界处理实现尺寸精确的电子束照射
公开(公告)号：US06271852B1
公开(公告)日：2001-08-07
申请号：US08856706
申请日：1997-05-15
申请人： Kinya Kamiyama , Koichi Moriizumi , Hironobu Taoka
发明人： Kinya Kamiyama , Koichi Moriizumi , Hironobu Taoka
IPC分类号： G06T1100
CPC分类号： H01J37/3026 , H01J2237/31764
摘要： A electron beam writing data creating device comprises a redundant part split means for splitting data into a redundant part formed by connecting redundant areas of graphic data processing areas with each other and an internal area defined in the graphic data processing area by the outer periphery of the redundant area. The redundant part split means splits design layout data into the redundant part and the internal area, for independently performing overlap removal processing in each area. Thus, a electron beam writing data creating device capable of effectively suppressing deterioration of dimensional accuracy of a writing pattern can be provided.
摘要翻译：电子束写入数据创建装置包括冗余部分拆分装置，用于将数据分割成通过将图形数据处理区域的冗余区域彼此连接而形成的冗余部分以及在图形数据处理区域中定义的内部区域冗余区域。冗余部分拆分装置将设计布局数据分割成冗余部分和内部区域，用于在每个区域中独立执行重叠移除处理。因此，可以提供能够有效地抑制写入图案的尺寸精度的劣化的电子束写入数据创建装置。

9. 发明授权

US08464192B2 Lithography verification apparatus and lithography simulation program 有权
标题翻译：平版印刷验证装置和光刻仿真程序
公开(公告)号：US08464192B2
公开(公告)日：2013-06-11
申请号：US13348431
申请日：2012-01-11
申请人： Hironobu Taoka
发明人： Hironobu Taoka
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70441 , G03F7/705
摘要： The present invention provides a lithography verification apparatus which executes high-precision lithography verification in consideration of the effects of individual errors integrated. Various information (simulation result, error standard, etc.) are input. A variation distribution value is calculated. The variation distribution value and a variation distribution error standard are compared to determine whether the variation distribution value is smaller than the error standard. The variation distribution error standard is a standard for a value or the like related to a standard deviation or the like for a dimensional displacement. When it is determined that the variation distribution value is smaller than the error standard, an error is determined not to exist, and the processing is ended. When it is determined that the variation distribution value is not smaller than the error standard, an error is determined to exist, and an error list and a variation distribution value are outputted.
摘要翻译：本发明提供一种光刻验证装置，其考虑到集成的各个误差的影响，执行高精度光刻验证。输入各种信息（模拟结果，误差标准等）。计算变化分布值。比较变异分布值和变异分布误差标准，确定变异分布值是否小于误差标准。变化分布误差标准是与尺寸位移的标准偏差等相关的值等的标准。当确定变化分布值小于误差标准时，确定不存在错误，并且处理结束。当确定变化分布值不小于误差标准时，确定存在错误，并且输出错误列表和变化分布值。

10. 发明授权

US6088520A Method of producing highly precise charged beam drawing data divided into plurality of drawing fields 失效
标题翻译：制造分割成多个绘图场的高精度带电束图的数据的方法
公开(公告)号：US6088520A
公开(公告)日：2000-07-11
申请号：US971132
申请日：1997-11-13
申请人： Hironobu Taoka , Kinya Kamiyama , Koichi Moriizumi
发明人： Hironobu Taoka , Kinya Kamiyama , Koichi Moriizumi
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01J37/302 , H01L21/027
CPC分类号： H01J37/3026 , H01J2237/31762 , H01J2237/31764
摘要： A method of producing charged beam drawing data includes a basic figure processing step of performing a basic figure processing to design layout data to output basic figure data, a first segmenting step of converting the basic figure data as if segmenting a basic figure over a boundary of a figure processing region in the basic figure data by the boundary, a first searching step of searching a minute figure to draw which satisfies a prescribed size condition among the figures produced by segmenting in said first segmenting step, a restoring step of integrating the minute figure to draw searched by said first searching step and a figure adjacent to the minute figure, and performing a further basic figure processing to restore the figures in said basic figure data, an allocating step of allocating the figures restored by said restoring step to drawing fields, and a step of converting the figures allocated by the allocating step to charged beam drawing data.
摘要翻译：一种产生带电波束绘图数据的方法包括：基本图形处理步骤，执行基本图形处理以设计布局数据以输出基本图形数据;第一分割步骤，转换基本图形数据，如同将基本图形分割为边界上的基本图形基于边界的基本图形数据中的图形处理区域，在所述第一分割步骤中通过分割生成的图形中搜索满足规定尺寸条件的微小图形的第一搜索步骤，通过所述第一搜索步骤绘制搜索和与所述微小图形相邻的图形，以及执行进一步的基本图形处理以恢复所述基本图形数据中的图形;分配步骤，将由所述恢复步骤恢复的图形分配给绘制区域，以及将由分配步骤分配的图形转换为带电波束绘制数据的步骤。

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