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1. 发明授权

US07969790B2 Method of erasing an NVM cell that utilizes a gated diode 有权
标题翻译：擦除使用门控二极管的NVM单元的方法
公开(公告)号：US07969790B2
公开(公告)日：2011-06-28
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译：一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开，包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

2. 发明申请

US20110007570A1 METHOD OF READING AN NVM CELL THAT UTILIZES A GATED DIODE 有权
标题翻译：读取使用栅极二极管的NVM电池的方法
公开(公告)号：US20110007570A1
公开(公告)日：2011-01-13
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译：一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。

3. 发明授权

US07978519B2 Method of reading an NVM cell that utilizes a gated diode 有权
标题翻译：读取利用门控二极管的NVM单元的方法
公开(公告)号：US07978519B2
公开(公告)日：2011-07-12
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译：一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。

4. 发明申请

US20110007574A1 METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE 有权
标题翻译：消除使用栅极二极管的NVM电池的方法
公开(公告)号：US20110007574A1
公开(公告)日：2011-01-13
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译：一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开，包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

5. 发明申请

US20090296493A1 MID-SIZE NVM CELL AND ARRAY UTILIZING GATED DIODE FOR LOW CURRENT PROGRAMMING 有权
标题翻译：用于低电流编程的中等尺寸NVM单元和阵列利用栅极二极管
公开(公告)号：US20090296493A1
公开(公告)日：2009-12-03
申请号：US12539872
申请日：2009-08-12
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided.
摘要翻译：提供了一种操作使用门控二极管的非易失性存储器（NVM）单元结构的方法。该单元架构使用大约4-10 um2每位，包括门控二极管，用于对单元进行编程，同时消耗低编程电流。单元架构还允许在同一时间编程大量单元，从而减少每位的有效编程时间。还提供擦除和读取模式偏置条件。

6. 发明授权

US07859912B2 Mid-size NVM cell and array utilizing gated diode for low current programming 有权
标题翻译：中等尺寸的NVM单元和阵列利用栅极二极管用于低电流编程
公开(公告)号：US07859912B2
公开(公告)日：2010-12-28
申请号：US12539872
申请日：2009-08-12
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided.
摘要翻译：提供了一种操作使用门控二极管的非易失性存储器（NVM）单元结构的方法。该单元架构使用大约4-10 um2每位，包括门控二极管，用于对单元进行编程，同时消耗低编程电流。单元结构还允许在同一时间编程大量单元，从而减少每位的有效编程时间。还提供擦除和读取模式偏置条件。

7. 发明授权

US07425741B1 EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion 有权
标题翻译：具有利用偏置金属板和导电层排除的具有改进的数据保留的EEPROM结构
公开(公告)号：US07425741B1
公开(公告)日：2008-09-16
申请号：US11186442
申请日：2005-07-21
申请人： Andrew Strachan , Natalia Lavrovskaya , Saurabh Desai , Roozbeh Parsa , Yuri Mirgorodski
发明人： Andrew Strachan , Natalia Lavrovskaya , Saurabh Desai , Roozbeh Parsa , Yuri Mirgorodski
IPC分类号： H01L29/788
CPC分类号： H01L29/4234 , H01L21/28273 , H01L29/66825
摘要： A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication process flow, but any biased conductive layer can be used.
摘要翻译：在NVM单元结构上提供偏置的导电板以克服由于在较高温度下导电的介电膜的存在而导致的数据保持电荷损失。偏置的导电板优选地由制造工艺流程中的最低金属层形成，但是可以使用任何偏置的导电层。

8. 发明授权

US07911869B1 Fuse-type memory cells based on irreversible snapback device 有权
标题翻译：基于不可逆快速恢复装置的保险丝型存储单元
公开(公告)号：US07911869B1
公开(公告)日：2011-03-22
申请号：US11198688
申请日：2005-08-05
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： G11C17/14 , G11C17/18 , G11C17/08 , H01H37/76 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
摘要翻译：在使用熔丝单元的可编程电路中，使用不具有可逆快速恢复能力的快速恢复NMOS或NPN晶体管或SCR作为反熔丝，并且编程包括偏置晶体管的控制电极以使晶体管进入快速恢复模式。

9. 发明授权

US07262401B2 Active pixel sensor cell with integrating varactor and method for using such cell 有权
标题翻译：具有积分变容二极管的有源像素传感器单元和使用这种单元的方法
公开(公告)号：US07262401B2
公开(公告)日：2007-08-28
申请号：US11496951
申请日：2006-08-01
申请人： Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
发明人： Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
摘要翻译：包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

10. 发明授权

US07057867B1 Electrostatic discharge (ESD) protection clamp circuitry 有权
标题翻译：静电放电（ESD）保护钳位电路
公开(公告)号：US07057867B1
公开(公告)日：2006-06-06
申请号：US10851516
申请日：2004-05-21
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： H02H9/00
CPC分类号： H01L27/0259 , H01L27/0266
摘要： Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal.
摘要翻译：静电放电（ESD）保护钳位电路，包括电流隧道电路，以提供控制电流，用于控制电流分流电路，用于从受保护的信号端子分流ESD电流。

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