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1. 发明授权

US07743278B2 Test access control for plural processors of an integrated circuit 有权
标题翻译：集成电路的多个处理器的测试访问控制
公开(公告)号：US07743278B2
公开(公告)日：2010-06-22
申请号：US11600208
申请日：2006-11-16
申请人： Yuri Ikeda , Yoshikazu Aoto , Jun Matsushima , Hiroyuki Sasaki , Tomoyoshi Ujii , Makoto Saen
发明人： Yuri Ikeda , Yoshikazu Aoto , Jun Matsushima , Hiroyuki Sasaki , Tomoyoshi Ujii , Makoto Saen
IPC分类号： G06F11/00
CPC分类号： G01R31/31705 , G01R31/318572
摘要： The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided. With the configuration, even in the case where the number of processors increases, the invention can flexibly address the increase.
摘要翻译：本发明旨在促进包括多个微处理器的半导体集成电路器件的调试。半导体集成电路装置包括：多个处理器; 多个调试接口，能够调试相应的处理器; 由所述多个调试接口共享的多个公共终端; 选择电路，其能够将所述多个调试接口选择性地连接到所述公共端子; 以及控制器，其能够根据预定指令来控制选择电路中的选择操作。提供能够选择性地将多个调试接口连接到符合JTAG规范的终端组中的TRST终端的第一选择器，并且提供能够选择性地将多个调试接口连接到除了TRST终端之外的终端的第二选择器。利用该配置，即使在处理器数量增加的情况下，本发明可以灵活地解决增加的问题。

2. 发明申请

US20070226558A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070226558A1
公开(公告)日：2007-09-27
申请号：US11600208
申请日：2006-11-16
申请人： Yuri Ikeda , Yoshikazu Aoto , Jun Matsushima , Hiroyuki Sasaki , Tomoyoshi Ujii , Makoto Saen
发明人： Yuri Ikeda , Yoshikazu Aoto , Jun Matsushima , Hiroyuki Sasaki , Tomoyoshi Ujii , Makoto Saen
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/318572
摘要： The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided. With the configuration, even in the case where the number of processors increases, the invention can flexibly address the increase.
摘要翻译：本发明旨在促进包括多个微处理器的半导体集成电路器件的调试。半导体集成电路装置包括：多个处理器; 多个调试接口，能够调试相应的处理器; 由所述多个调试接口共享的多个公共终端; 选择电路，其能够将所述多个调试接口选择性地连接到所述公共端子; 以及控制器，其能够根据预定指令来控制选择电路中的选择操作。提供能够选择性地将多个调试接口连接到符合JTAG规范的终端组中的TRST终端的第一选择器，并且提供能够选择性地将多个调试接口连接到除了TRST终端之外的终端的第二选择器。利用该配置，即使在处理器数量增加的情况下，本发明可以灵活地解决增加的问题。

3. 发明授权

US06055651A Emulator and corresponding trace control method 失效
标题翻译：仿真器及相应的跟踪控制方法
公开(公告)号：US06055651A
公开(公告)日：2000-04-25
申请号：US763318
申请日：1996-12-10
申请人： Hiroyuki Sasaki , Yoshikazu Aoto , Shuya Fujita , Tatsuya Suzuki
发明人： Hiroyuki Sasaki , Yoshikazu Aoto , Shuya Fujita , Tatsuya Suzuki
IPC分类号： G06F11/28 , G06F11/00 , G06F11/22 , G06F11/34 , G06F11/36 , G06F11/30
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/348
摘要： A trace memory in the emulator is formed into a plurality of memory banks. Data to be traced is in principle stored sequentially in each memory bank. A trace condition setting circuit (trace registers) and a trace condition agreement detecting circuit (comparators) are provided to generate a valid/invalid flag FB indicating whether or not the data meet the set condition. This flag FB is stored along with the trace data in each memory bank.
摘要翻译：仿真器中的跟踪存储器形成为多个存储体。要跟踪的数据原则上按顺序存储在每个存储体中。提供跟踪条件设置电路（跟踪寄存器）和跟踪条件协议检测电路（比较器）以产生指示数据是否满足设置条件的有效/无效标志FB。该标志FB与跟踪数据一起存储在每个存储体中。

4. 发明授权

US5493659A Data processor providing fast break in program execution 失效
标题翻译：数据处理器在程序执行中提供快速突破
公开(公告)号：US5493659A
公开(公告)日：1996-02-20
申请号：US626740
申请日：1990-12-13
申请人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
发明人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
IPC分类号： G06F11/36 , G06F9/44 , G06F9/46
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.
摘要翻译：在处理器中设置有响应于外部提供的信号切换输入存储电路中保持的SWI指令的电路，由此可以使用这样的内部电路来实现对程序字的替换，从而高速并且可以实现程序执行的可靠中断。此外，通过设置指定的操作模式来建立与正常中断分离的中断功能，由此当使用数据处理器作为仿真器时，可以通过利用特殊中断来容易地实现包括普通中断处理的用户程序的中断功能。此外，通过附加地提供表示中断状态的信号的功能，可以简化外部电路。

5. 发明授权

US5644703A Data processor providing fast break in program execution 失效
标题翻译：数据处理器在程序执行中提供快速突破
公开(公告)号：US5644703A
公开(公告)日：1997-07-01
申请号：US554805
申请日：1995-11-07
申请人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
发明人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
IPC分类号： G06F11/36 , G06F9/44 , G06F9/46
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.
摘要翻译：在处理器中设置有响应于外部提供的信号切换输入存储电路中保持的SWI指令的电路，由此可以使用这样的内部电路来实现对程序字的替换，从而高速并且可以实现程序执行的可靠中断。此外，通过设置指定的操作模式来建立与正常中断分离的中断功能，由此当使用数据处理器作为仿真器时，可以通过利用特殊中断来容易地实现包括普通中断处理的用户程序的中断功能。此外，通过附加地提供表示中断状态的信号的功能，可以简化外部电路。

6. 发明授权

US4998197A Data processor with fast break in program execution by selectively processing either external control signal or external interrupt 失效
标题翻译：数据处理器通过选择性地处理外部控制信号或外部中断来快速中断程序执行
公开(公告)号：US4998197A
公开(公告)日：1991-03-05
申请号：US215506
申请日：1988-07-06
申请人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
发明人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
IPC分类号： G06F11/36
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program excution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

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