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1. 发明授权

US06333531B1 Dopant control of semiconductor devices 失效
标题翻译：半导体器件的掺杂剂控制
公开(公告)号：US06333531B1
公开(公告)日：2001-12-25
申请号：US09239655
申请日：1999-01-29
申请人： Yun-Yu Wang , Johnathan E. Faltermeier , Philip L. Flaitz , Jeffery L. Hurd , Rajarao Jammy , Radhika Srinivasan , Francis G. Trudeau , Dinah S. Weiss
发明人： Yun-Yu Wang , Johnathan E. Faltermeier , Philip L. Flaitz , Jeffery L. Hurd , Rajarao Jammy , Radhika Srinivasan , Francis G. Trudeau , Dinah S. Weiss
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.
摘要翻译：在邻近异种材料的界面附近的半导体器件内的材料中形成小晶粒结构的工艺，导致高扩散晶粒结构。在一种材料内部形成的高度扩散的晶粒结构增强了掺杂杂质的扩散，并提供了在相邻不同材料中的改进的掺杂剂控制。

2. 发明授权

US06194736B1 Quantum conductive recrystallization barrier layers 失效
标题翻译：量子导电重结晶阻挡层
公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。量子导电层优选用于沟槽电容器中以用作再结晶屏障。

3. 发明授权

US06339007B1 Capacitor stack structure and method of fabricating description 失效
标题翻译：电容器堆叠结构及其制造方法
公开(公告)号：US06339007B1
公开(公告)日：2002-01-15
申请号：US09562556
申请日：2000-05-02
申请人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
发明人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
IPC分类号： H01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.
摘要翻译：一种电容器结构，其包括顶部铂电极和在电极的侧壁上具有绝缘体的底部电极，并且其中底部电极从沉积相对于绝缘体在其侧壁上凹进的第一电极部分并且沉积第二绝缘体提供部分。

4. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

5. 发明申请

US20080254643A1 STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER 有权
标题翻译：结构提高顶级CVD低K电介质和介电吸收层之间的粘合力
公开(公告)号：US20080254643A1
公开(公告)日：2008-10-16
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

6. 发明授权

US07402532B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07402532B2
公开(公告)日：2008-07-22
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

7. 发明授权

US07820559B2 Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer 有权
标题翻译：用于改善顶部CVD低K电介质和介电顶盖层之间粘合的结构
公开(公告)号：US07820559B2
公开(公告)日：2010-10-26
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/31 , H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘附过渡层包括下部含SiO x或SiON的区域和上部C分级区域。还提供了形成这种结构，特别是粘附过渡层的方法。

8. 发明授权

US08368069B2 Antifuse structure for in line circuit modification 有权
公开(公告)号：US08368069B2
公开(公告)日：2013-02-05
申请号：US13360270
申请日：2012-01-27
申请人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

9. 发明授权

US08294485B2 Detecting asymmetrical transistor leakage defects 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US08294485B2
公开(公告)日：2012-10-23
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： G01R31/02 , G01R31/08
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.
摘要翻译：检测大晶体管阵列（例如大量SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如，SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。

10. 发明申请

US20120184075A1 REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION 失效
标题翻译：通过目标碳植入减少半导体器件中的分离形成
公开(公告)号：US20120184075A1
公开(公告)日：2012-07-19
申请号：US13009020
申请日：2011-01-19
申请人： Anthony G. Domenicucci , Shreesh Narasimha , Karen A. Nummy , Viorel C. Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Shreesh Narasimha , Karen A. Nummy , Viorel C. Ontalus , Yun-Yu Wang
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
摘要翻译：形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。这消除了导致设备泄漏失败的缺陷。

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