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1. 发明授权

US07682450B2 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US07682450B2
公开(公告)日：2010-03-23
申请号：US11485323
申请日：2006-07-13
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： C30B21/02
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅，以及填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

2. 发明授权

US08419853B2 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US08419853B2
公开(公告)日：2013-04-16
申请号：US12623515
申请日：2009-11-23
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： C30B21/04
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

3. 发明授权

US07585757B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07585757B2
公开(公告)日：2009-09-08
申请号：US11446151
申请日：2006-06-05
申请人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
发明人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53271 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
摘要翻译：在制造半导体器件的半导体器件和方法中，在绝缘层上形成防穿透膜图案和沟道膜图案。穿透防止图案和绝缘层可以分别包括氮化物和氧化物。穿透防止图案位于通道图案下方。

4. 发明申请

US20060281290A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060281290A1
公开(公告)日：2006-12-14
申请号：US11446151
申请日：2006-06-05
申请人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
发明人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53271 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.

5. 发明申请

US20070023794A1 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US20070023794A1
公开(公告)日：2007-02-01
申请号：US11485323
申请日：2006-07-13
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

6. 发明申请

US20080087933A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080087933A1
公开(公告)日：2008-04-17
申请号：US11905035
申请日：2007-09-27
申请人： Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Jong-Seon Ahn
发明人： Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Jong-Seon Ahn
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11 , B82Y10/00 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： Example embodiments relate to a semiconductor memory device including a channel layer pattern on a substrate, the channel layer pattern having a sidewall and an upper face, a spacer on the sidewall of the channel layer pattern, and a gate electrode covering the sidewall of the channel layer pattern, the spacer and the upper face of the channel layer pattern.
摘要翻译：示例性实施例涉及包括衬底上的沟道层图案，沟道层图案具有侧壁和上表面的半导体存储器件，沟道层图案的侧壁上的间隔物，以及覆盖沟道侧壁的栅电极层图案，间隔物和沟道层图案的上表面。

7. 发明授权

US07268029B2 Method of fabricating CMOS transistor that prevents gate thinning 有权
标题翻译：制造防止栅极薄化的CMOS晶体管的方法
公开(公告)号：US07268029B2
公开(公告)日：2007-09-11
申请号：US10994042
申请日：2004-11-19
申请人： Eun-kuk Chung , Joon Kim , Suk-Chul Bang , Jong-Sun Ahn , Sang-hoon Lee , Woo-soon Jang , Yung-jun Kim
发明人： Eun-kuk Chung , Joon Kim , Suk-Chul Bang , Jong-Sun Ahn , Sang-hoon Lee , Woo-soon Jang , Yung-jun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/31111 , H01L21/31144
摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.
摘要翻译：提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由构图多晶硅层。用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

8. 发明申请

US20050112814A1 Method of fabricating CMOS transistor that prevents gate thinning 有权
标题翻译：制造防止栅极薄化的CMOS晶体管的方法
公开(公告)号：US20050112814A1
公开(公告)日：2005-05-26
申请号：US10994042
申请日：2004-11-19
申请人： Eun-kuk Chung , Joon Kim , Suk-Chul Bang , Jong-Sun Ahn , Sang-hoon Lee , Woo-soon Jang , Yung-jun Kim
发明人： Eun-kuk Chung , Joon Kim , Suk-Chul Bang , Jong-Sun Ahn , Sang-hoon Lee , Woo-soon Jang , Yung-jun Kim
IPC分类号： H01L21/311 , H01L21/8238 , H01L21/00 , H01L21/302 , H01L21/461 , H01L21/8234 , H01L21/84
CPC分类号： H01L21/823842 , H01L21/31111 , H01L21/31144
摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.
摘要翻译：提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由构图多晶硅层。用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

9. 发明申请

US20080176374A1 METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELF-ALIGNED METAL SHUNTS 审中-公开
标题翻译：使用自对准金属层形成半导体器件的方法
公开(公告)号：US20080176374A1
公开(公告)日：2008-07-24
申请号：US12018469
申请日：2008-01-23
申请人： Yeol Jon , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim
发明人： Yeol Jon , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L21/823437 , H01L21/76897 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L27/11 , H01L29/66545
摘要： A method of fabricating a semiconductor device using a self-aligned metal shunt process is disclosed. The method can include sequentially forming a lower conductive pattern and a sacrificial pattern on a semiconductor substrate. An interlayer dielectric layer is formed to cover the sacrificial pattern. The interlayer dielectric layer is patterned to form a preliminary trench that exposes the top surface of the sacrificial pattern. The exposed sacrificial pattern is removed to form a trench that expose the top surface of the lower conductive pattern. An upper conductive pattern is formed to fill the trench.
摘要翻译：公开了使用自对准金属分流工艺制造半导体器件的方法。该方法可以包括在半导体衬底上顺序地形成下导电图案和牺牲图案。形成层间电介质层以覆盖牺牲图案。图案化层间电介质层以形成暴露牺牲图案的顶表面的预备沟槽。去除暴露的牺牲图案以形成暴露下导电图案的顶表面的沟槽。形成上部导电图案以填充沟槽。

10. 发明授权

US07049197B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07049197B2
公开(公告)日：2006-05-23
申请号：US10976680
申请日：2004-10-28
申请人： Woo-Soon Jang , Joon Kim , Eun-Kuk Chung
发明人： Woo-Soon Jang , Joon Kim , Eun-Kuk Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11 , H01L27/1104
摘要： In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.
摘要翻译：在制造包括彼此分离的独立栅极图案的半导体器件的方法中，通过在衬底上形成场区来限定有源区。在基板上形成栅氧化层和多晶硅层。通过第一蚀刻工艺沿着第一方向部分去除多晶硅层来形成初步栅极图案。沿着初步栅极图案的侧表面形成间隔物。通过第二蚀刻工艺沿着与第一方向交叉的第二方向部分地去除预选栅极图案来形成多个分离的栅极图案。栅极图案与有源区域重叠并且彼此分离。因此，重叠余量增加，并且当图案化以形成栅极图案时，防止多晶硅层被过度蚀刻。

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