专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080254642A1 METHOD OF FABRICATING GATE DIELECTRIC LAYER 审中-公开
标题翻译：制造电介质层的方法
公开(公告)号：US20080254642A1
公开(公告)日：2008-10-16
申请号：US11735916
申请日：2007-04-16
申请人： Yun-Ren Wang , Ying-Wei Yen , Chien-Liang Lin , Shu-Yen Chan
发明人： Yun-Ren Wang , Ying-Wei Yen , Chien-Liang Lin , Shu-Yen Chan
IPC分类号： H01L21/31
CPC分类号： H01L21/31662 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/02332 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/318 , H01L21/823462 , H01L29/518
摘要： A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate.
摘要翻译：提供一种制造栅极介电层的方法。首先，在基板上形成牺牲层。接着，将氟离子注入基板。然后，除去牺牲层。最后，在基板上形成电介质层。

2. 发明授权

US07601404B2 Method for switching decoupled plasma nitridation processes of different doses 有权
标题翻译：用于切换不同剂量的去耦等离子体氮化过程的方法
公开(公告)号：US07601404B2
公开(公告)日：2009-10-13
申请号：US11160108
申请日：2005-06-09
申请人： Ying-Wei Yen , Yun-Ren Wang , Shu-Yen Chan , Chen-Kuo Chiang , Chung-Yih Chen
发明人： Ying-Wei Yen , Yun-Ren Wang , Shu-Yen Chan , Chen-Kuo Chiang , Chung-Yih Chen
IPC分类号： B05D3/02 , C23C16/34
CPC分类号： H01J37/321 , H01J2237/3387 , H01L21/3145
摘要： A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.
摘要翻译：提供了能够减少切换时间的切换不同剂量的去耦等离子体氮化（DPN）过程的方法。根据该方法，将虚设晶片插入到室内，将引入的工艺气体点燃到等离子体中，然后在虚设晶片上进行下一剂量的DPN掺杂工序。因此，腔室的氮浓度被快速调整以转换到下一剂量的DPN过程。此外，在重复上述步骤的几个循环之后，将虚设晶片插入到腔室中，并且在虚拟晶片上执行下一剂量的完整DPN处理。该过程在切换到下一个DPN过程之前进行几次。

3. 发明申请

US20060280876A1 Method for Switching Decoupled Plasma Nitridation Processes of Different Doses 有权
标题翻译：用于切换不同剂量的去耦等离子体氮化过程的方法
公开(公告)号：US20060280876A1
公开(公告)日：2006-12-14
申请号：US11160108
申请日：2005-06-09
申请人： Ying-Wei Yen , Yun-Ren Wang , Shu-Yen Chan , Chen-Kuo Chiang , Chung-Yih Chen
发明人： Ying-Wei Yen , Yun-Ren Wang , Shu-Yen Chan , Chen-Kuo Chiang , Chung-Yih Chen
IPC分类号： H05H1/24
CPC分类号： H01J37/321 , H01J2237/3387 , H01L21/3145
摘要： A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.
摘要翻译：提供了能够减少切换时间的切换不同剂量的去耦等离子体氮化（DPN）过程的方法。根据该方法，将虚设晶片插入到室内，将引入的工艺气体点燃到等离子体中，然后在虚设晶片上进行下一剂量的DPN掺杂工序。因此，腔室的氮浓度被快速调整以转换到下一剂量的DPN过程。此外，在重复上述步骤的几个循环之后，将虚设晶片插入到腔室中，并且在虚拟晶片上执行下一剂量的完整DPN处理。该过程在切换到下一个DPN过程之前进行几次。

4. 发明申请

US20060014350A1 METHOD FOR FABRICATING A SEMICONDUCTOR TRANSISTOR DEVICE HAVING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS 审中-公开
标题翻译：制造具有超声波源/漏极延伸的半导体晶体管器件的方法
公开(公告)号：US20060014350A1
公开(公告)日：2006-01-19
申请号：US10710521
申请日：2004-07-18
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan
IPC分类号： H01L21/336 , H01L21/331 , H01L21/425
CPC分类号： H01L29/6656 , H01L21/265 , H01L21/823814 , H01L29/6659 , H01L29/7842 , H01L29/7843
摘要： A method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions is provided. A silicon substrate having thereon a poly gate structure is prepared. The poly gate structure has sidewalls and a top surface. An offset spacer is formed on its sidewall. An ion implantation process is carried out to form an ultra-shallow junction doping region in the silicon substrate next to the offset spacer. An oxide liner is deposited on the offset spacer and on the top surface of the poly gate structure. A tensile nitride spacer layer is then deposited on the oxide liner. A stress modification implantation process is performed to turn the tensile nitride spacer layer into a more compressive status. A dry etching process is then carried out to etch the nitride spacer layer so as to form a spacer.
摘要翻译：提供了一种制造具有超浅源极/漏极延伸部分的半导体晶体管器件的方法。制备其上具有多晶硅结构的硅衬底。多晶硅结构具有侧壁和顶表面。在其侧壁上形成偏移间隔物。进行离子注入工艺以在邻近偏移间隔物的硅衬底中形成超浅结掺杂区域。氧化物衬垫沉积在偏移间隔物和多晶硅栅极结构的顶表面上。然后在氧化物衬垫上沉积拉伸氮化物间隔层。执行应力改变注入工艺以将拉伸氮化物间隔层转变成更压缩状态。然后进行干蚀刻工艺以蚀刻氮化物间隔层以便形成间隔物。

5. 发明申请

US20070082506A1 MULTI-STEP ANNEALING PROCESS 有权
标题翻译：多步骤退火工艺
公开(公告)号：US20070082506A1
公开(公告)日：2007-04-12
申请号：US11308508
申请日：2006-03-31
申请人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02337 , H01L21/02318 , H01L21/02329 , H01L21/0234 , H01L21/324 , H01L21/823462 , H01L29/66537 , H01L29/78
摘要： A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.
摘要翻译：描述制造介电层的方法。提供衬底，并且在衬底上形成电介质层。介电层通过氮化处理进行。介电层通过第一退火工艺进行。在第一退火工艺中使用的第一种气体包括惰性气体和氧气。第一气体具有惰性气体与氧的第一分压比。介电层通过第二退火工艺进行。在第二退火中使用的第二气体包括惰性气体和氧气。第二气体具有惰性气体与氧气的第二分压比，第二分压比小于第一分压比。两个退火工艺的至少一个退火温度等于或大于950℃。本发明改善了分布在介电层中的氮掺杂剂的均匀性。

6. 发明申请

US20080318405A1 METHOD OF FABRICATING GATE STRUCTURE 有权
标题翻译：制造门式结构的方法
公开(公告)号：US20080318405A1
公开(公告)日：2008-12-25
申请号：US12192128
申请日：2008-08-15
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

7. 发明申请

US20070082503A1 METHOD OF FABRICATING A DIELECTRIC LAYER 审中-公开
标题翻译：制作电介质层的方法
公开(公告)号：US20070082503A1
公开(公告)日：2007-04-12
申请号：US11163218
申请日：2005-10-11
申请人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/3144
摘要： A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.
摘要翻译：描述制造介电层的方法。提供衬底，并且在衬底上形成电介质层。介电层通过氮化处理进行。介电层通过第一退火工艺进行。在第一退火工艺中使用的第一种气体包括惰性气体和氧气。第一气体具有惰性气体与氧的第一分压比。介电层通过第二退火工艺进行。在第二退火中使用的第二气体包括惰性气体和氧气。第二气体具有惰性气体与氧气的第二分压比，第二分压比小于第一分压比。两个退火工艺的至少一个退火温度等于或大于950℃。本发明改善了分布在介电层中的氮掺杂剂的均匀性。

8. 发明授权

US07811892B2 Multi-step annealing process 有权
标题翻译：多步退火工艺
公开(公告)号：US07811892B2
公开(公告)日：2010-10-12
申请号：US11308508
申请日：2006-03-31
申请人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Chien-Hua Lung , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/477
CPC分类号： H01L21/02337 , H01L21/02318 , H01L21/02329 , H01L21/0234 , H01L21/324 , H01L21/823462 , H01L29/66537 , H01L29/78
摘要： A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.
摘要翻译：描述制造介电层的方法。提供衬底，并且在衬底上形成电介质层。介电层通过氮化处理进行。介电层通过第一退火工艺进行。在第一退火工艺中使用的第一种气体包括惰性气体和氧气。第一气体具有惰性气体与氧的第一分压比。介电层通过第二退火工艺进行。在第二退火中使用的第二气体包括惰性气体和氧气。第二气体具有惰性气体与氧气的第二分压比，第二分压比小于第一分压比。两个退火工艺的至少一个退火温度等于或大于950℃。本发明改善了分布在介电层中的氮掺杂剂的均匀性。

9. 发明授权

US07709316B2 Method of fabricating gate structure 有权
标题翻译：栅极结构的制作方法
公开(公告)号：US07709316B2
公开(公告)日：2010-05-04
申请号：US12192128
申请日：2008-08-15
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L21/8249
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

10. 发明申请

US20070102774A1 GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：门结构及其制作方法
公开(公告)号：US20070102774A1
公开(公告)日：2007-05-10
申请号：US11164025
申请日：2005-11-08
申请人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
发明人： Yun-Ren Wang , Ying-Wei Yen , Shu-Yen Chan , Kuo-Tai Huang
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28202 , H01L21/28088 , H01L21/76822 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
摘要翻译：提供一种制造栅极结构的方法。首先，在基板上形成牺牲氧化物层。进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。接下来，除去牺牲氧化物层。进行再氧化处理以在衬底的表面上产生界面层。在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式