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1. 发明授权

US6103633A Method for cleaning metal precipitates in semiconductor processes 失效
标题翻译：在半导体工艺中清洗金属沉淀物的方法
公开(公告)号：US6103633A
公开(公告)日：2000-08-15
申请号：US977190
申请日：1997-11-24
申请人： Yun-Hung Shen , Sheng-Liang Pan
发明人： Yun-Hung Shen , Sheng-Liang Pan
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76862 , H01L21/32051 , H01L21/3213 , H01L21/76841 , H01L21/76858
摘要： A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer wherein metal precipitates form at the interface between the barrier metal layer and the metal layer. The metal layer is covered with a layer of photoresist which is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby the metal precipitates are exposed on the surface of the barrier metal layer. The barrier metal layer is anisotropically etched into using a high DC bias of greater than 240 volts and thereafter isotropically etched into underlying the metal precipitates whereby the metal precipitates are stripped away from the surface of the barrier metal layer completing the cleaning of the metal precipitates in the formation of metal lines in the fabrication of an integrated circuit.
摘要翻译：描述了在使用两步法蚀刻金属线之后清洗金属沉淀物的新方法。半导体器件结构设置在半导体衬底中和半导体衬底上。半导体器件结构被绝缘层覆盖。覆盖在绝缘层上的阻挡金属层被沉积。金属层沉积在阻挡金属层上，其中金属沉淀物在阻挡金属层和金属层之间的界面处形成。金属层被一层光致抗蚀剂覆盖，该光致抗蚀剂暴露于光化光并显影和图案化以形成所需的光致抗蚀剂掩模。金属层被蚀刻掉，其未被光致抗蚀剂掩模覆盖以形成金属线，由此金属沉淀物暴露在阻挡金属层的表面上。阻挡金属层被各向异性地蚀刻成使用大于240伏特的高直流偏压，然后各向同性蚀刻到金属沉淀物的下面，从而将金属沉淀物从阻挡金属层的表面剥离，完成金属沉淀物的清洁在制造集成电路中形成金属线。

2. 发明授权

US5776832A Anti-corrosion etch process for etching metal interconnections extending over and within contact openings 失效
标题翻译：用于蚀刻在接触开口之上和之内延伸的金属互连的防蚀刻蚀刻工艺
公开(公告)号：US5776832A
公开(公告)日：1998-07-07
申请号：US682481
申请日：1996-07-17
申请人： Chia-Dar Hsieh , Yun-Hung Shen , Sheng-Liang Pan , Jen Song Liu
发明人： Chia-Dar Hsieh , Yun-Hung Shen , Sheng-Liang Pan , Jen Song Liu
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/31
CPC分类号： H01L21/02071
摘要： A method for anti-corrosion etching of metal interconnections, comprised in part of an aluminum layer, is achieved. The metal lines form self-aligned contacts (SAC) in contact openings in a polysilicon/metal dielectric (PMD) layer to a patterned underlying polysilicon layer. The method involves performing an oxygen ashing step in the same etching chamber immediately after etching the aluminum lines in a halogen gas, such as BCl.sub.3 and Cl.sub.2. This method using oxygen ashing avoids the use of the more traditional passivation gases CHF.sub.3 and CF.sub.4 which can overetch the polysilicon exposed in the SAC process that would cause electrical opens. And further, it avoids the formation of a polymer residue which is difficult to remove. The oxygen treatment reduces the Cl.sub.2 on the sidewalls of the Al lines, and also removes portions of the photoresist mask material containing Cl.sub.2. It is also easier to remove the remaining photoresist in a solvent stripping process. SEM measurements of the etch bias of the photoresist critical dimension also indicate the formation of a redeposition on the Al sidewalls which further protects the Al from corrosion when the wafers are removed from the etch chamber and are exposed to moisture.
摘要翻译：实现了在铝层的一部分中包含金属互连的抗腐蚀蚀刻的方法。金属线在多晶硅/金属电介质（PMD）层的接触开口中形成自对准接触（SAC）到图案化的下层多晶硅层。该方法包括在蚀刻卤素气体如BCl 3和Cl 2中的铝线之后立即在相同的蚀刻室中进行氧化灰化步骤。这种使用氧灰的方法避免使用更传统的钝化气体CHF3和CF4，其可以过蚀刻在SAC工艺中暴露的将导致电气打开的多晶硅。此外，它避免了难以除去的聚合物残余物的形成。氧处理减少了Al线的侧壁上的Cl2，并且还去除了含有Cl 2的光致抗蚀剂掩模材料的部分。在溶剂汽提过程中也更容易除去剩余的光致抗蚀剂。光致抗蚀剂临界尺寸的蚀刻偏差的SEM测量也表明在Al侧壁上形成再沉积，当晶片从蚀刻室中移除并暴露于湿气时，Al侧壁进一步保护Al免受腐蚀。

3. 发明授权

US07071032B2 Material to improve image sensor yield during wafer sawing 失效
标题翻译：材料可以提高晶圆锯切时的图像传感器产量
公开(公告)号：US07071032B2
公开(公告)日：2006-07-04
申请号：US10431275
申请日：2003-05-07
申请人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan , Fu-Tien Weng
发明人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan , Fu-Tien Weng
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/6836 , H01L21/78 , H01L27/14683 , H01L2221/68327
摘要： A new method is provided of treating the wafer prior to the process of singulating the wafer into individual die. A first surface of the wafer over which CMOS image sensor devices have been created is coated with a layer of material that is non-soluble in water. The wafer is attached to a tape by bringing a second surface of the wafer in contact with the tape. The wafer is singulated by approaching the first surface of the wafer and by sawing first through the layer of material that has been coated over the first surface of the wafer and by then sawing through the wafer, stopping at the surface of the tape. A thorough water rinse is applied to the surface of the singulated wafer, followed by a wafer clean applying specific chemicals for this purpose. The singulated die is now removed from the tape and further processed by applying steps of die mount, wire bonding, surrounding the die in a mold compound and marking the package.
摘要翻译：提供了一种新的方法，在将晶片分离成单独的芯片的过程之前处理晶片。已经在其上形成CMOS图像传感器装置的晶片的第一表面涂覆有不溶于水的材料层。通过使晶片的第二表面与带接触而将晶片附接到带。通过接近晶片的第一表面并通过首先穿过已经涂覆在晶片的第一表面上的材料层，然后通过晶片锯切，停止在带的表面，将晶片分离。将彻底的水冲洗施加到单片晶片的表面，接着进行晶片清洁以应用特定的化学品用于此目的。单片模具现在从胶带中取出并通过将模具安装，引线接合，将模具包围在模具化合物中并标记包装件的步骤进一步处理。

4. 发明授权

US07009772B2 High transmittance overcoat for microlens arrays in semiconductor color imagers 有权
标题翻译：用于半导体彩色成像器中的微透镜阵列的高透射率外涂层
公开(公告)号：US07009772B2
公开(公告)日：2006-03-07
申请号：US10957920
申请日：2004-10-04
申请人： Yu-Kung Hsiao , Sheng-Liang Pan , Bii-Juno Chang , Kuo-Liang Lu
发明人： Yu-Kung Hsiao , Sheng-Liang Pan , Bii-Juno Chang , Kuo-Liang Lu
IPC分类号： G02B27/10
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14623 , H01L31/02327
摘要： A transmittance overcoat with effectively planar top surface and specified optical and materials properties is applied above a microlens layer to extend the focal length and enhance the performance of long focal length microlenses for semiconductor array color imaging devices. The geometrical optics design factors and microelectric fabrication sequence to achieve optimized long focal length microlens performance are disclosed. The principal advantages of the adaptive process taught in the present invention is shown to enable real-time compensation adjustments for process and material variations. The overcoat process enables simplified single-layer integrated microlens optics for low-cost, high volume manufacturing of CMOS and CCD color video cameras.
摘要翻译：在微透镜层之上施加具有有效平面顶表面和特定光学和材料特性的透光率外涂层以延长焦距并增强半导体阵列彩色成像装置的长焦距微透镜的性能。公开了实现优化的长焦距微透镜性能的几何光学设计因子和微电子制造序列。示出了本发明中教导的自适应过程的主要优点，以实现对过程和材料变化的实时补偿调整。外涂层工艺可实现简化的单层集成微透镜光学器件，用于CMOS和CCD彩色摄像机的低成本，大批量制造。

5. 发明授权

US06971270B2 Method and apparatus for measuring gripping strength of a vacuum wand 失效
标题翻译：用于测量真空棒的夹紧强度的方法和装置
公开(公告)号：US06971270B2
公开(公告)日：2005-12-06
申请号：US10782036
申请日：2004-02-19
申请人： Ruei-Hung Jang , Chih-Lin Ying , Tsung-Chi Hsieh , Sheng-Liang Pan , Ching-Hui Tai
发明人： Ruei-Hung Jang , Chih-Lin Ying , Tsung-Chi Hsieh , Sheng-Liang Pan , Ching-Hui Tai
IPC分类号： G01L1/00 , G01L5/00 , G01L5/22 , G01L7/00
CPC分类号： G01L5/0033 , G01L5/226
摘要： A method and apparatus for measuring the vacuum gripping strength of a vacuum wand or robotic arm provides a pressure gauge and a conduit extending from the pressure gauge and terminating at an opening formed in a receiving surface. A vacuum wand head is positioned on the receiving surface such that the gripping surface of the vacuum wand forms a conterminous boundary with the receiving surface and the vacuum port of the vacuum wand is aligned over the opening formed in the receiving surface. The receiving surface replicates a wafer surface so that the same vacuum gripping strength as would be delivered to a wafer being gripped by the vacuum wand, is thereby sensed by the pressure gauge. Spring loaded positioning members act in conjunction with a clamp member and a mechanical stop position the vacuum wand head in the receiving area and over the opening and also to assure that the gripping surface of the vacuum wand head is flush against the surface of the receiving area. Diminution of vacuum gripping strength caused by scratches or other defects of the gripping surface that cause vacuum leaks between gripping surface and the wafer surface, are similarly reproduced and sensed by the pressure gauge.
摘要翻译：用于测量真空棒或机器人手臂的真空夹紧强度的方法和装置提供压力计和从压力计延伸并终止于形成在接收表面中的开口的导管。真空棒头定位在接收表面上，使得真空棒的抓握表面与接收表面形成一个连续的边界，并且真空棒的真空端口在形成在接收表面中的开口上对准。接收表面复制晶片表面，从而通过压力计感测到与由真空棒夹持的晶片相同的真空夹紧强度。弹簧加载的定位构件与夹紧构件一起作用并且机械地将真空棒头位于接收区域中并在开口上并且还确保真空棒头的夹持表面与接收区域的表面齐平。通过压力计类似地再现和感测由夹紧表面上的擦伤或其他缺陷导致抓握表面和晶片表面之间的真空泄漏的真空夹紧强度的减小。

6. 发明授权

US06926818B1 Method to enhance the adhesion between dry film and seed metal 有权
标题翻译：提高干膜和种子金属之间粘附的方法
公开(公告)号：US06926818B1
公开(公告)日：2005-08-09
申请号：US09961557
申请日：2001-09-24
申请人： Yih-Ann Lin , Tung-Heng Shie , Kai-Ming Ching , Sheng-Liang Pan , Kuo-Liang Lu
发明人： Yih-Ann Lin , Tung-Heng Shie , Kai-Ming Ching , Sheng-Liang Pan , Kuo-Liang Lu
IPC分类号： C25D5/02
CPC分类号： C25D5/022 , H01L2224/0401 , H01L2224/05557
摘要： A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug. The patterned dry film resist is removed from the conductive structure. The conductive plug is reflowed to form the bump structure.
摘要翻译：通过使用电镀液形成凸点结构的方法，包括以下步骤。提供具有上覆导电结构的基板。在导电结构上形成图案化的干膜抗蚀剂。图案化的干膜抗蚀剂具有暴露导电结构的一部分的沟槽。在界面处附着在导电结构上的图案化的干膜抗蚀剂。通过增加图案化的干膜抗蚀剂在界面处的导电结构的粘附性的处理来处理该结构。通过使用电镀溶液，导电插塞在沟槽内的导电结构的暴露部分之上。图案化的干膜抗蚀剂在界面处增加了对导电结构的粘附，防止电镀溶液在形成导电插塞期间渗透图案化的干膜抗蚀剂和导电结构的界面。从导电结构去除图案化的干膜抗蚀剂。导电塞被回流以形成凸块结构。

7. 发明授权

US06586322B1 Method of making a bump on a substrate using multiple photoresist layers 有权
标题翻译：使用多个光致抗蚀剂层在基板上制造凸块的方法
公开(公告)号：US06586322B1
公开(公告)日：2003-07-01
申请号：US10032341
申请日：2001-12-21
申请人： Chih-Cheng Chiu , Sheng-Liang Pan , Kuo-Liang Lu
发明人： Chih-Cheng Chiu , Sheng-Liang Pan , Kuo-Liang Lu
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05166 , H01L2224/05655 , H01L2224/1147 , H01L2224/11474 , H01L2224/11849 , H01L2224/11902 , H01L2224/11914 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the step of providing a semiconductor device having a contact pad and an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A first photoresist layer is deposited in a liquid state so that the first photoresist layer covers the under bump metallurgy. A second photoresist layer is deposited and the second photoresist layer is a dry film photoresist. The unexposed portions of the first photoresist layer are removed. The remaining portions of the first photoresist layers are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.
摘要翻译：在半导体晶片或倒装芯片等基板上形成凸点的方法。该方法包括提供具有接触焊盘和上钝化层的半导体器件的步骤，以及形成在上钝化层中的开口，露出接触焊盘的一部分。在上钝化层和接触焊盘上沉积凸块下冶金。以液态沉积第一光致抗蚀剂层，使得第一光致抗蚀剂层覆盖凸块下金属。沉积第二光致抗蚀剂层，第二光致抗蚀剂层是干膜光致抗蚀剂。去除第一光致抗蚀剂层的未曝光部分。去除第一光致抗蚀剂层的剩余部分。导电材料被重熔以在半导体器件上提供凸块。

8. 发明授权

US06281140B1 Method of reducing the roughness of a gate insulator layer after exposure of the gate insulator layer to a threshold voltage implantation procedure 有权
标题翻译：在栅极绝缘体层暴露于阈值电压注入程序之后减小栅极绝缘体层的粗糙度的方法
公开(公告)号：US06281140B1
公开(公告)日：2001-08-28
申请号：US09591846
申请日：2000-06-12
申请人： Chie-Chi Chen , Sheng-Liang Pan
发明人： Chie-Chi Chen , Sheng-Liang Pan
IPC分类号： H01L214763
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/3105 , H01L21/31105
摘要： A process for reducing the surface roughness of a silicon dioxide gate insulator layer, that has been subjected to a boron ion implantation procedure, has been developed. The process features the use of an ammonium hydroxide-hydrogen peroxide solution, applied to the gate insulator layer, to reduce the surface roughness of the gate insulator layer, created by the boron ion implantation procedure. The treatment of the gate insulator layer, in the ammonium hydroxide-hydrogen peroxide solution, results in a surface roughness equivalent to the surface roughness of the gate insulator layer, prior to the boron ion implantation procedure.
摘要翻译：已经开发了一种用于降低二氧化硅栅极绝缘体层的已经经过硼离子注入工艺的表面粗糙度的方法。该方法的特征在于使用施加到栅极绝缘体层的氢氧化铵 - 过氧化氢溶液，以减少由硼离子注入程序产生的栅极绝缘体层的表面粗糙度。在硼离子注入程序之前，在氢氧化铵 - 过氧化氢溶液中处理栅极绝缘体层导致与栅极绝缘体层的表面粗糙度相当的表面粗糙度。

9. 发明授权

US07838386B2 Method and system for patterning alignment marks on a transparent substrate 有权
标题翻译：在透明基板上图案化对准标记的方法和系统
公开(公告)号：US07838386B2
公开(公告)日：2010-11-23
申请号：US12235960
申请日：2008-09-23
申请人： Ruei-Hung Jang , Ya-Wen Lee , Tzu-Yang Wu , Sheng-Liang Pan , Chin-Hsiang Lin , Tsai-Sheng Gau
发明人： Ruei-Hung Jang , Ya-Wen Lee , Tzu-Yang Wu , Sheng-Liang Pan , Chin-Hsiang Lin , Tsai-Sheng Gau
IPC分类号： H01L21/76 , H01L21/00 , H01L23/544
CPC分类号： G02B26/0841
摘要： Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.
摘要翻译：公开了一种在透明基板上形成对准标记的方法和系统。光反射层沉积在晶片的光学透明衬底上。围绕光学透明基板上的对准标记限定区域。除了该区域之外，从透明基板的大部分除去光反射层。另外，公开了一种微电子机械系统装置。该器件包括光学透明衬底，在光学透明衬底上的至少一个光学部分透明的对准标记，以及附接到光学透明衬底的多个反射元件或成像像素。

10. 发明申请

US20070249137A1 Method and system for wafer backside alignment 失效
标题翻译：晶圆背面对准的方法和系统
公开(公告)号：US20070249137A1
公开(公告)日：2007-10-25
申请号：US11409582
申请日：2006-04-24
申请人： Sheng-Chieh Liu , Chia-Hung Kao , Tzu-Yang Wu , Sheng-Liang Pan , Yuan-Bang Lee
发明人： Sheng-Chieh Liu , Chia-Hung Kao , Tzu-Yang Wu , Sheng-Liang Pan , Yuan-Bang Lee
IPC分类号： H01L21/306 , H01L21/76 , H01L21/302
CPC分类号： B81C1/00603
摘要： Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.
摘要翻译：公开了一种用于晶片背面对准的方法和系统。在基板的正面上形成零标记。多个层沉积在基板的正面上。将晶片的背面朝上翻转，从背面到沉积在基板前侧的蚀刻停止层进行贯通晶片蚀刻。

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