专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5623100A Ultrasonic inspection and imaging intstrument 失效
标题翻译：超声波检查和成像仪器
公开(公告)号：US5623100A
公开(公告)日：1997-04-22
申请号：US505535
申请日：1995-07-21
申请人： Yukio Arima , Toshihiro Kimura , Yuichi Kunitomo , Tadatoshi Shimamura , Takeshi Nishiduka , Ken Takeuchi
发明人： Yukio Arima , Toshihiro Kimura , Yuichi Kunitomo , Tadatoshi Shimamura , Takeshi Nishiduka , Ken Takeuchi
IPC分类号： G01N29/06 , G01N29/24 , G01N29/34 , G01N29/38 , G01S15/89
CPC分类号： G01S15/8906 , G01N29/0645 , G01N29/2456 , G01N29/343 , G01N29/345 , G01N29/38 , G01N29/4454 , G01N29/4463 , G01N2291/011 , G01N2291/02854 , G01N2291/0423 , G01N2291/2697
摘要： In an ultrasonic inspection and imaging instrument, a pulse generator and a burst wave generator are provided in association with the activation of an ultrasonic probe by the pulse generator and in response to a measurement value obtained from a signal reception circuit portion. A first gate position is obtained with regard to an inspection portion in a sample, and then a second gate position for a burst wave measurement is set by correcting the first gate position. The burst wave measurement is performed by activating the burst wave generator.
摘要翻译：在超声波检查和成像仪器中，与通过脉冲发生器激活超声波探头并响应于从信号接收电路部分获得的测量值相关联地提供脉冲发生器和脉冲波发生器。关于样本中的检查部分获得第一门位置，然后通过校正第一门位置来设置用于突发波测量的第二门位置。突发波测量通过激活脉冲串波发生器来执行。

2. 发明授权

US08687400B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US08687400B2
公开(公告)日：2014-04-01
申请号：US13684407
申请日：2012-11-23
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C5/06
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

3. 发明授权

US08677217B2 Data input / output control device and semiconductor memory device system 有权
标题翻译：数据输入/输出控制装置和半导体存储器件系统
公开(公告)号：US08677217B2
公开(公告)日：2014-03-18
申请号：US13087035
申请日：2011-04-14
申请人： Ken Takeuchi , Shuhei Tanakamaru
发明人： Ken Takeuchi , Shuhei Tanakamaru
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C7/1006 , G11C2029/0411
摘要： When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit 32 (step S100 and S110). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.
摘要翻译：当检测到的错误数据数Nerr超过上限误差Nmax时，存储器控制器的纠错电路存储与存储的数据长度相同的两倍长的数据长度作为执行Sdata的数据长度作为校正信息存储单元中的执行数据长度Sdata ，并且代码长度Scref比执行数据长度Sdata长，并且比校正信息存储单元32中执行代码长度的错误上限数目多（步骤S100和S110）可检测到的错误数。错误校正电路使用具有用于执行Scode的存储代码长度的BCH码，使用半导体存储器件中存储的编码数据的半导体存储器件中存储的编码数据的BCH码对输入数据进行编码，使用BCH码对输入数据执行纠错，并且解码纠错数据

4. 发明授权

US08635511B2 Data processing apparatus, control device and data storage device 有权
标题翻译：数据处理装置，控制装置和数据存储装置
公开(公告)号：US08635511B2
公开(公告)日：2014-01-21
申请号：US13205239
申请日：2011-08-08
申请人： Ken Takeuchi , Mayumi Fukuda
发明人： Ken Takeuchi , Mayumi Fukuda
IPC分类号： G11C29/00
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C11/005 , G11C13/0002 , G11C13/0033 , G11C13/0069 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.
摘要翻译：当写入数据D是高重写数据时，PC 10控制DRAM24以存储写入数据D（步骤S100和S110）。当写入数据D不是高重写数据时，PC 10将一个RRAM写入请求信号和写入数据D输出到一个SSD（步骤S100和S120）。 SSD的存储器控制器输入RRAM写入请求信号控制RRAM和SRAM以将写数据D存储在RRAM或SRAM中。这种处理使得存储在DRAM中的数据能够被频繁地重写。因此，可以实现DRAM的刷新操作次数的减少和功耗的降低。

5. 发明授权

US08259494B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
公开(公告)号：US08259494B2
公开(公告)日：2012-09-04
申请号：US12855507
申请日：2010-08-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

6. 发明申请

US20110170355A1 SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF CHIPS AND CAPABILITY OF OUTPUTTING A BUSY SIGNAL 有权
标题翻译：半导体存储器件具有多重的信号和输出一个繁忙信号的能力
公开(公告)号：US20110170355A1
公开(公告)日：2011-07-14
申请号：US13071729
申请日：2011-03-25
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

7. 发明授权

US07933134B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US07933134B2
公开(公告)日：2011-04-26
申请号：US11904565
申请日：2007-09-27
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C5/06
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

8. 发明申请

US20100226173A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100226173A1
公开(公告)日：2010-09-09
申请号：US12781396
申请日：2010-05-17
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

9. 发明授权

US07633826B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07633826B2
公开(公告)日：2009-12-15
申请号：US11938756
申请日：2007-11-12
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

10. 发明授权

US07596042B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
公开(公告)号：US07596042B2
公开(公告)日：2009-09-29
申请号：US11906379
申请日：2007-10-02
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C7/00
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式