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    • 3. 发明授权
    • Semiconductor memory device and method of performing data reduction test
    • 半导体存储器件和执行数据压缩测试的方法
    • US07907433B2
    • 2011-03-15
    • US12385949
    • 2009-04-24
    • Hideo NomuraTomonori HayashiYuji Sugiyama
    • Hideo NomuraTomonori HayashiYuji Sugiyama
    • G11C5/02
    • G11C7/1045G11C29/1201G11C29/48G11C2207/105H01L25/0657H01L2924/0002H01L2924/30105H01L2924/00
    • A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
    • 一种半导体器件,包括封装中包含的多个封装端子,设置在封装上的多个芯片,每个芯片包括存储单元阵列和多个数据输入/输出端子,以及多个数据线控制开关 设置在多个封装端子与多个数据输入/输出端子之间。 每个芯片的多个数据线控制开关以正常模式将每个芯片的数据输入/输出端子连接到多个封装端子中的相应的一个。 多个数据线控制开关在测试模式中将不同芯片中的数据输入/输出端子的不同组连接到封装端子的各组。 数据输入/输出端子的各组属于多个数据输入/输出端子。 封装端子的各组在不同的芯片之间是不同的。
    • 4. 发明授权
    • Infrared light irradiating lamp for vehicle
    • 车载红外线照明灯
    • US07618170B2
    • 2009-11-17
    • US11890568
    • 2007-08-07
    • Yuji SugiyamaShigeyuki WatanabeShoichiro YokoiAtsushi SugimotoHideki Fukuchi
    • Yuji SugiyamaShigeyuki WatanabeShoichiro YokoiAtsushi SugimotoHideki Fukuchi
    • F21V11/00B60Q1/00F21V9/00
    • F21S41/13F21V9/40
    • An infrared light irradiating lamp for a vehicle includes a projection lens disposed on an optical axis extending in a longitudinal direction of the vehicle, a light source bulb disposed behind a rear focal point of the projection lens, a reflector for reflecting light emitted from the light source bulb in a forward direction close to the optical axis by setting the light source bulb as a first focal point of the reflector, a filter driving unit disposed between the projection lens and the light source bulb, the filter driving unit having a movable shaft to be driven in a vertical direction, a bracket having a tip portion and a base end, the tip portion holding an infrared light transmitting filter, and a rotating shaft disposed between the movable shaft to the base end of the bracket for linking the movable shaft to the base end.
    • 一种用于车辆的红外线照射灯包括设置在沿着车辆的纵向方向延伸的光轴上的投影透镜,设置在投影透镜的后焦点后面的光源灯泡,用于反射从光发射的光的反射器 通过将所述光源灯泡设置为所述反射器的第一焦点,沿着靠近所述光轴的向前方向的光源灯泡,设置在所述投影透镜和所述光源灯泡之间的滤光器驱动单元,所述滤光器驱动单元具有可动轴, 沿垂直方向被驱动,具有尖端部分和基端的托架,保持红外透光滤光片的尖端部分和设置在可移动轴到支架的基端之间的旋转轴,用于将可动轴连接到 基端
    • 7. 发明授权
    • Fail memory circuit and interleave copy method of the same
    • 故障存储器电路和交错复制方法相同
    • US06219287B1
    • 2001-04-17
    • US09671126
    • 2000-09-27
    • Yuji Sugiyama
    • Yuji Sugiyama
    • G11C700
    • G11C29/44G11C7/1006G11C7/1018G11C2029/1208
    • The address generation circuit 10 generates the address in which the fail data is stored. The logical circuit 15 comprises: when the address is inputted, a circuit to delay the address by a predetermined constant time; a circuit to output the selection signal which is the binary level signal; and a circuit to output the signal inputted from the address generation circuit 10 or the signal inputted from the pipe line circuit, corresponding to the value of the selection signal. When the address is inputted, the memory array 16 outputs the fail data stored in the address of the memory units A -D, or writes the inputted fail data in address of the memory units A -D. The OR circuit 70 OR-operates a plurality of inputted fail data, and outputs to the memory array 16.
    • 地址生成电路10生成存储故障数据的地址。 逻辑电路15包括:当地址被输入时,将地址延迟预定的恒定时间的电路; 输出作为二进制电平信号的选择信号的电路; 以及电路,输出从地址产生电路10输入的信号或从管线电路输入的信号,对应于选择信号的值。 当输入地址时,存储器阵列16输出存储在存储器单元A-D的地址中的故障数据,或将输入的故障数据写入到存储器单元A-D的地址中。 或电路70或者操作多个输入的故障数据,并将其输出到存储器阵列16。
    • 8. 发明授权
    • Flat tablet case with a hinged cap
    • 扁平平板盒带铰链盖
    • US5947294A
    • 1999-09-07
    • US338
    • 1998-01-20
    • Katsuhiko OmataYuji SugiyamaMikiko SuzukiHisashi Aizawa
    • Katsuhiko OmataYuji SugiyamaMikiko SuzukiHisashi Aizawa
    • A45C11/24B65D83/04B65D83/06G09F3/20
    • G09F3/20A45C11/24B65D83/0481
    • A flat tablet case (A) is assembled by joining together a bottom half case (30) having the shape of a rectangular tray and a top half case (10) having the shape of a rectangular tray. A plurality of studs (21 to 25) are formed on the inner surface of the top half case (10), and a plurality of sockets (41 to 45) are formed on the inner surface the bottom half case (30). A hinged cap (50) is formed integrally with the bottom half case (30) in a section of the side wall (31) excluding corners. The hinged cap (50) is provided on its opposite side surfaces with projections (53, 54) which are engaged with and disengaged from cap holding structures (35, 36) formed on the bottom half case (30).
    • PCT No.PCT / JP97 / 01793 Sec。 371日期1998年1月20日 102(e)1998年1月20日PCT PCT 1997年5月27日PCT公布。 公开号WO97 / 45337 日期1997年12月4日通过将具有矩形托盘的形状的下半壳(30)和具有矩形托盘形状的上半壳(10)接合在一起组装平板式箱(A)。 在上半壳体(10)的内表面上形成多个螺柱(21至25),并且在下半壳体(30)的内​​表面上形成多个插座(41至45)。 在侧壁(31)的不包括拐角的部分中,铰接盖(50)与下半壳(30)整体形成。 铰链盖(50)在其相对的侧表面上设置有与形成在下半壳(30)上的盖保持结构(35,36)接合并脱离的突起(53,54)。
    • 10. 发明授权
    • Semiconductor memory device performing refresh operation and method of testing the same
    • 执行刷新操作的半导体存储器件及其测试方法
    • US08363496B2
    • 2013-01-29
    • US12805238
    • 2010-07-20
    • Tomonori HayashiAkihiko KagamiYuji Sugiyama
    • Tomonori HayashiAkihiko KagamiYuji Sugiyama
    • G11C29/08G11C7/00
    • G11C11/406G11C11/401G11C29/02G11C29/023G11C29/50016
    • A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.
    • 一种半导体存储器件,包括掩模信息存储电路,其存储指示在存储单元阵列中的多个区域中表示不进行自刷新操作的区域的掩模信息,由自刷新命令激活的掩模确定电路 并且响应于刷新地址和掩模信息之间的匹配的检测而产生匹配信号,以及响应于匹配信号的激活而禁用自刷新操作的刷新操作控制电路。 当测试模式信号被激活时,掩模确定电路也被自动刷新命令激活。 利用这种配置,可以在不实际进入自刷新模式的情况下执行部分阵列自刷新功能的测试。