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1. 发明授权

US4688392A Refrigeration unit including a hot gas defrosting system 失效
标题翻译：制冷单元包括热气除霜系统
公开(公告)号：US4688392A
公开(公告)日：1987-08-25
申请号：US857315
申请日：1986-04-30
申请人： Yuji Fujimoto , Masayuki Aono , Tsutomu Takei , Tetuo Nakano , Teiji Nakabayashi
发明人： Yuji Fujimoto , Masayuki Aono , Tsutomu Takei , Tetuo Nakano , Teiji Nakabayashi
IPC分类号： F25B47/02 , F25B41/00 , F25D21/06
CPC分类号： F25B47/022
摘要： A refrigeration unit comprising a cooling circuit having a compressor, a condenser and an evaporator, and said unit including a hot gas valve and a hot gas bypass passage bypassing the condenser and forming a defrost circuit, so that when the evaporator is frosted upon operation by means of the cooling circuit, constant quantity refrigerant is circulated around the defrost circuit to perform a defrosting operation.

2. 发明授权

US4602485A Refrigeration unit including a hot gas defrosting system 失效
标题翻译：制冷单元包括热气除霜系统
公开(公告)号：US4602485A
公开(公告)日：1986-07-29
申请号：US601014
申请日：1984-04-16
申请人： Yuji Fujimoto , Masayuki Aono , Tsutomu Takei , Tetuo Nakano , Teiji Nakabayashi
发明人： Yuji Fujimoto , Masayuki Aono , Tsutomu Takei , Tetuo Nakano , Teiji Nakabayashi
IPC分类号： F25B47/02 , F25B41/00 , F25B47/00
CPC分类号： F25B47/022
摘要： A refrigeration unit comprising a cooling circuit having a compressor, a condenser and an evaporator, and said unit including a hot gas valve and a hot gas bypass passage bypassing the condenser and forming a defrost circuit, so that when the evaporator is frosted upon operation by means of the cooling circuit, constant quantity refrigerant is circulated around the defrost circuit to perform a defrosting operation.
摘要翻译：一种制冷单元，包括具有压缩机，冷凝器和蒸发器的冷却回路，并且所述单元包括旁通冷凝器的热气阀和热气旁通通道，并形成除霜回路，使得当蒸发器在运行时结霜冷却回路的装置，恒定量的制冷剂在除霜回路周围循环，进行除霜运转。

3. 发明授权

US07617469B2 Assertion description conversion device, method and computer program product 失效
标题翻译：断言描述转换装置，方法和计算机程序产品
公开(公告)号：US07617469B2
公开(公告)日：2009-11-10
申请号：US11842317
申请日：2007-08-21
申请人： Tsutomu Takei , Hiroshi Imai
发明人： Tsutomu Takei , Hiroshi Imai
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the verification target in a design description of a broader term; verification target description conversion unit converting the description of the verification target into a design description of a narrower term according to the design description of the narrower term corresponding to the description searched by the design description searching unit; verification content analysis unit for analyzing verification contents for the verification target described in the high-level assertion description; and verification content description conversion unit for converting the verification contents analyzed by the verification content analysis unit into the description format of a low-level assertion description language for verification of a design description of the narrower term.
摘要翻译：一种断言描述转换装置，包括：验证目标识别单元，解析由高级断言描述语言描述的高级别断言描述的语法，用于验证输入的更广泛术语的设计描述以识别验证目标; 设计描述搜索单元在更广泛的术语的设计描述中搜索验证目标的描述; 验证对象描述转换单元根据与由设计描述搜索单元搜索的描述相对应的较窄项的设计描述将验证目标的描述转换为较窄项的设计描述; 验证内容分析单元，用于分析在高级别断言描述中描述的验证目标的验证内容; 以及验证内容描述转换单元，用于将由验证内容分析单元分析的验证内容转换为用于验证较窄项目的设计描述的低级断言描述语言的描述格式。

4. 发明申请

US20080059928A1 ASSERTION DESCRIPTION CONVERSION DEVICE, METHOD AND COMPUTER PROGRAM PRODUCT 失效
标题翻译：说明转换装置，方法和计算机程序产品
公开(公告)号：US20080059928A1
公开(公告)日：2008-03-06
申请号：US11842317
申请日：2007-08-21
申请人： Tsutomu Takei , Hiroshi Imai
发明人： Tsutomu Takei , Hiroshi Imai
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the verification target in a design description of a broader term; verification target description conversion unit converting the description of the verification target into a design description of a narrower term according to the design description of the narrower term corresponding to the description searched by the design description searching unit; verification content analysis unit for analyzing verification contents for the verification target described in the high-level assertion description; and verification content description conversion unit for converting the verification contents analyzed by the verification content analysis unit into the description format of a low-level assertion description language for verification of a design description of the narrower term.
摘要翻译：一种断言描述转换装置，包括：验证目标识别单元，解析由高级断言描述语言描述的高级别断言描述的语法，用于验证输入的更广泛术语的设计描述以识别验证目标; 设计描述搜索单元在更广泛的术语的设计描述中搜索验证目标的描述; 验证对象描述转换单元根据与由设计描述搜索单元搜索的描述相对应的较窄项的设计描述将验证目标的描述转换为较窄项的设计描述; 验证内容分析单元，用于分析在高级别断言描述中描述的验证目标的验证内容; 以及验证内容描述转换单元，用于将由验证内容分析单元分析的验证内容转换为用于验证较窄项目的设计描述的低级断言描述语言的描述格式。

5. 发明申请

US20070074141A1 Simulation apparatus and simulation method 审中-公开
标题翻译：仿真设备及仿真方法
公开(公告)号：US20070074141A1
公开(公告)日：2007-03-29
申请号：US11527418
申请日：2006-09-27
申请人： Tsutomu Takei
发明人： Tsutomu Takei
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to an aspect of the invention, a simulation apparatus includes: a computer configured to execute a program which is formed as an operating description having no temporal restriction; and a programmable circuit configured to be on which a designing object circuit configured to perform a cycle operation is mounted. The programmable circuit includes; a data transfer circuit configured to transfer data between the computer and the designing subject circuit in a unit of a transaction; a verification circuit configured to verify as to whether or not operation of the designing subject circuit satisfies a specification and notifying a detection of an error when the operation of the designing subject circuit does not satisfy the specification; and a verification result transfer circuit configured to temporarily stop the operation of the designing subject circuit in the case that the detection of the error is notified so as to transfer a verification result obtained by the verification circuit to the computer.
摘要翻译：根据本发明的一个方面，一种模拟装置包括：计算机，被配置为执行形成为没有时间限制的操作描述的程序; 以及被配置为在其上安装被配置为执行循环操作的设计对象电路的可编程电路。可编程电路包括：数据传输电路，被配置为以交易为单位在计算机和设计对象电路之间传送数据; 验证电路，被配置为验证所述设计对象电路的操作是否满足规格，并且当所述设计对象电路的操作不满足所述规范时，通知所述错误的检测; 以及验证结果传送电路，其被配置为在通知所述错误的检测以便将由所述验证电路获得的验证结果传送到所述计算机的情况下暂时停止所述设计对象电路的操作。

6. 发明授权

US5930147A Design support system in which delay is estimated from HDL description 失效
标题翻译：设计支持系统，其中从HDL描述估计延迟
公开(公告)号：US5930147A
公开(公告)日：1999-07-27
申请号：US724471
申请日：1996-10-01
申请人： Tsutomu Takei
发明人： Tsutomu Takei
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5045
摘要： A design support device 1 has a module division and merger section 8 for receiving a result from a HDL analysis section 6 to analyze a HDL description of a RTL and for dividing and merging the modules based on instructions from outside or automatically, a module allocation section 10 for allocating the modules by using the result from the module division and merger section 8 and the analyzed result by the HDL analysis section 6, a budgeting section 11 for budgeting an area, a shape, a timing, and a power consumption to each of the modules allocated by the module allocation means 10, and an estimation section for estimating module information for the result from the module division and merger section 8 and the result from the module allocation section 10.
摘要翻译：设计支持装置1具有模块划分和合并部分8，用于从HDL分析部分6接收结果，以分析RTL的HDL描述，并且基于来自外部或自动的指令来分割和合并模块，模块分配部分 10，用于通过使用模块分割和合并部分8的结果以及HDL分析部分6的分析结果来分配模块，用于将每个的区域，形状，时间和功耗预算的预算部分11 由模块分配装置10分配的模块以及用于从模块划分和合并部分8估计结果的模块信息和模块分配部分10的结果的估计部分。

7. 发明授权

US07418681B2 Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit 失效
标题翻译：用于验证半导体集成电路逻辑特性的仿真系统，仿真方法和仿真程序
公开(公告)号：US07418681B2
公开(公告)日：2008-08-26
申请号：US11193836
申请日：2005-07-28
申请人： Tsutomu Takei
发明人： Tsutomu Takei
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an analyzing unit dividing a logic behavior of the semiconductor integrated circuit into a software-based first logic behavior and a hardware-based second logic behavior and generating circuit data of the interface circuit included in the first logic behavior that exhibits an input/output behavior and circuit data of the logic circuit that exhibits the second logic behavior.
摘要翻译：用于验证半导体集成电路的逻辑行为的模拟系统包括具有接口电路和逻辑电路的可再编程半导体器件; 以及分析单元，将半导体集成电路的逻辑行为分为基于软件的第一逻辑行为和基于硬件的第二逻辑行为，并且生成包括在表现出输入/输出行为的第一逻辑行为中的接口电路的电路数据以及呈现第二逻辑特性的逻辑电路的电路数据。

8. 发明申请

US20060052994A1 Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit 失效
标题翻译：用于验证半导体集成电路逻辑特性的仿真系统，仿真方法和仿真程序
公开(公告)号：US20060052994A1
公开(公告)日：2006-03-09
申请号：US11193836
申请日：2005-07-28
申请人： Tsutomu Takei
发明人： Tsutomu Takei
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an analyzing unit dividing a logic behavior of the semiconductor integrated circuit into a software-based first logic behavior and a hardware-based second logic behavior and generating circuit data of the interface circuit included in the first logic behavior that exhibits an input/output behavior and circuit data of the logic circuit that exhibits the second logic behavior.
摘要翻译：用于验证半导体集成电路的逻辑行为的模拟系统包括具有接口电路和逻辑电路的可再编程半导体器件; 以及分析单元，将半导体集成电路的逻辑行为分为基于软件的第一逻辑行为和基于硬件的第二逻辑行为，并且生成包括在表现出输入/输出行为的第一逻辑行为中的接口电路的电路数据以及呈现第二逻辑特性的逻辑电路的电路数据。

9. 发明授权

US5282146A Test assistant system for logical design process 失效
标题翻译：用于逻辑设计过程的测试助理系统
公开(公告)号：US5282146A
公开(公告)日：1994-01-25
申请号：US694136
申请日：1991-05-01
申请人： Masami Aihara , Masatoshi Sekine , Tsutomu Takei , Hiroaki Nishi , Kazuyoshi Kohno , Takeshi Kitahara , Atsushi Masuda
发明人： Masami Aihara , Masatoshi Sekine , Tsutomu Takei , Hiroaki Nishi , Kazuyoshi Kohno , Takeshi Kitahara , Atsushi Masuda
IPC分类号： G06F11/25 , G01R31/3183 , G06F17/50 , G06F15/60
CPC分类号： G01R31/318357 , G01R31/318307 , G06F17/5022
摘要： Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.
摘要翻译：公开了一种用于逻辑设计过程的测试辅助系统，包括用于存储表示要测试的电路组件的逻辑功能的语句的描述存储数据库，用于编译语句以输出对象数据的编译器，用于存储对象数据的数据库，用于通过使用存储在数据库中的对象数据来生成测试模式的测试模式发生器，用于存储测试模式的测试模式数据库，每个具有级别号码，用于通过使用测试执行用于逻辑功能的模拟的模拟器存储在测试模式数据库中的模式，以及用于显示对象数据，测试模式，模拟中使用的信息以及它们之间的关系的显示。数据库包括用于存储表示语句的语句对应表的区域，作为对电路组件的逻辑功能的描述的区域，用于存储表示对应于语句中描述的功能的电路组件的电路组件表的区域，用于存储表示语句之间的依赖关系的依赖关系表和表示语句对应表与电路分量表之间的对应关系的对应关系表。

10. 发明授权

US5218692A Digital pulse timing parameter measuring device 失效
标题翻译：数字脉冲定时参数测量装置
公开(公告)号：US5218692A
公开(公告)日：1993-06-08
申请号：US546450
申请日：1990-07-03
申请人： Yasuo Yamada , Katsuhisa Kondo , Tsutomu Takei , Masafumi Takahashi
发明人： Yasuo Yamada , Katsuhisa Kondo , Tsutomu Takei , Masafumi Takahashi
IPC分类号： G06F5/08
CPC分类号： G06F5/08
摘要： A pulse input device has a standard time generator for outputting standard time information by counting a system clock signal; an input circuit for sampling input signal information from a plurality of channels in synchronization with the standard time information at a predetermined period; a memory for storing the input signal information sampled by the input circuit; a command memory for storing a plurality of instruction commands; and a controller for scanning the instruction commands stored in the command memory to successively execute the instruction commands, for repeating the scanning operation of the instruction commands, and for controlling operations of the device. The controller outputs a designation signal having a period of a predetermined time for designating an execution starting time obtained by counting the system clock signals, so that the period of the execution starting time for each of the instruction commands becomes a constant rate in the successive command scanning operation for successively executing each of the instruction commands in synchronization with the designation signal, and the period of the predetermined time is set based on the instruction command having the longest execution time.
摘要翻译：脉冲输入装置具有标准时间发生器，用于通过对系统时钟信号进行计数来输出标准时间信息; 输入电路，用于以预定周期与所述标准时间信息同步地从多个信道中采样输入信号信息; 存储器，用于存储由输入电路采样的输入信号信息; 用于存储多个指令命令的命令存储器; 以及控制器，用于扫描存储在命令存储器中的指令命令，以连续执行指令命令，用于重复指令命令的扫描操作以及用于控制设备的操作。控制器输出具有预定时间的周期的指定信号，用于指定通过对系统时钟信号进行计数而获得的执行开始时间，使得每个指令命令的执行开始时间的周期在连续命令中变为恒定速率扫描操作，用于与指定信号同步地连续执行每个指令命令，并且基于具有最长执行时间的指令命令来设置预定时间的周期。

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