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    • 1. 发明授权
    • Capacitive load driving circuit and liquid crystal display
    • 电容负载驱动电路和液晶显示器
    • US07064945B2
    • 2006-06-20
    • US10728789
    • 2003-12-08
    • Yuji AmanoYoshio NirasawaHideo Hamaguchi
    • Yuji AmanoYoshio NirasawaHideo Hamaguchi
    • H02H9/02
    • H02H3/087
    • An output circuit may include a power supply terminal, a ground terminal, and an output terminal connected to a capacitive load. Depending on the state of a load control input signal, the output circuit performs selectively a charging-current supplying operation of supplying a charging-current from the power supply terminal to the capacitive load and a discharging-current withdrawing operation of withdrawing a discharging-current from the capacitive load to the ground terminal. An overcharging-current prevention switch is provided to detect a short circuit between the output terminal and the ground terminal so as to stop or suppress the charging-current supplying operation. An overdischarging-current prevention switch is provided to detect a short circuit between the output terminal and the power supply terminal so as to stop or suppress the discharging-current withdrawing operation.
    • 输出电路可以包括电源端子,接地端子和连接到电容负载的输出端子。 根据负载控制输入信号的状态,输出电路选择性地进行从电源端子向电容性负载提供充电电流的充电电流供给动作以及取出放电电流的放电电流取出动作 从容性负载到接地端子。 提供了一种过充电电流防止开关,用于检测输出端子和接地端子之间的短路,以便停止或抑制充电电流供应操作。 提供过放电电流防止开关来检测输出端子和电源端子之间的短路,以便停止或抑制放电电流取出操作。
    • 4. 发明授权
    • PLL circuit and image display device
    • PLL电路和图像显示装置
    • US07049867B2
    • 2006-05-23
    • US10915340
    • 2004-08-11
    • Norihide KinugasaYoshio NirasawaHideo HamaguchiSachi Ota
    • Norihide KinugasaYoshio NirasawaHideo HamaguchiSachi Ota
    • H03L7/06
    • H03L7/18H03L7/1803
    • A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
    • 使得压控振荡器在短时间内收敛到稳定状态的PLL电路,并且即使在提供参考输入信号的周期期间发生不连续性,也产生具有高稳定性的时钟信号。 PLL电路具有压控振荡器,用于输出时钟控制,第一计数器由参考输入信号复位,该参考输入信号在用于输出第一信号的预定周期内比参考周期长一个周期;第二计数器,用于输出第二信号 ,用于复位第二计数器的复位脉冲发生电路,用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号比参考值更长的不连续输入检测部分 期。
    • 5. 发明申请
    • PLL circuit and image display device
    • PLL电路和图像显示装置
    • US20050040872A1
    • 2005-02-24
    • US10915340
    • 2004-08-11
    • Norihide KinugasaYoshio NirasawaHideo HamaguchiSachi Ota
    • Norihide KinugasaYoshio NirasawaHideo HamaguchiSachi Ota
    • H04N5/06H03L7/08H03L7/14H03L7/18H03L7/06
    • H03L7/18H03L7/1803
    • The present invention provides a PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal. The PLL circuit of the present invention has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
    • 本发明提供一种使电压控制振荡器在短时间内收敛到稳定状态的PLL电路,即使在参考输入信号的周期中发生不连续性,也产生高稳定性的时钟信号。 本发明的PLL电路具有电压控制振荡器,用于输出时钟控制,第一计数器由参考输入信号复位,该参考输入信号在预定周期内具有比参考周期长一个周期,用于输出第一信号;第二计数器, 输出第二信号,用于复位第二计数器的复位脉冲发生电路,用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号的不连续输入检测部分 比参考期长。