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1. 发明申请

US20140008666A1 SILICON CARBIDE VERTICAL FIELD EFFECT TRANSISTOR 有权
标题翻译：碳化钨垂直场效应晶体管
公开(公告)号：US20140008666A1
公开(公告)日：2014-01-09
申请号：US14006548
申请日：2012-04-06
申请人： Yuichi Harada , Shinsuke Harada , Yasuyuki Hoshi , Noriyuki Iwamuro
发明人： Yuichi Harada , Shinsuke Harada , Yasuyuki Hoshi , Noriyuki Iwamuro
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/0615 , H01L29/0626 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7802 , H01L29/7808 , H01L29/7827
摘要： A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer.
摘要翻译：碳化硅垂直场效应晶体管包括第一导电型碳化硅衬底; 形成在第一导电型碳化硅衬底的表面上的低浓度第一导电型碳化硅层; 选择性地形成在第一导电型碳化硅层的表面上的第二导电型区域; 形成在第二导电型区域中的第一导电型源极区域; 形成在第二导电型区域中的第一导电型源极区域之间的高浓度第二导电型区域; 与高浓度第二导电型区域电连接的源电极和第一导电型源极区域; 由形成在相邻的第二导电型区域的第一导电型源极区域形成在第二导电型区域和第一导电型碳化硅层上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及在第一导电型碳化硅衬底的背侧上的漏电极，其中雪崩产生单元设置在第二导电型区域和第一导电型碳化硅层之间。

2. 发明授权

US07723817B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07723817B2
公开(公告)日：2010-05-25
申请号：US11420779
申请日：2006-05-29
申请人： Hiroshi Kanemaru , Naoki Kumagai , Yuichi Harada , Yoshihiro Ikura , Yoshiaki Minoya
发明人： Hiroshi Kanemaru , Naoki Kumagai , Yuichi Harada , Yoshihiro Ikura , Yoshiaki Minoya
IPC分类号： H01L29/00
CPC分类号： H01L21/76283 , H01L21/76275 , H01L21/823878 , H01L21/84 , H01L27/12 , H01L29/78603
摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
摘要翻译：绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达背面。这消除了在形成在背面的绝缘体膜与n型半导体衬底之间的界面中引入的表面状态的影响，由此可获得优异的击穿电压。

3. 发明授权

US06278140B1 Insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管
公开(公告)号：US06278140B1
公开(公告)日：2001-08-21
申请号：US09511167
申请日：2000-02-24
申请人： Yuichi Harada , Noriyuki Iwamuro , Tadayoshi Iwaana
发明人： Yuichi Harada , Noriyuki Iwamuro , Tadayoshi Iwaana
IPC分类号： H01L2974
CPC分类号： H01L29/0692 , H01L29/7455 , H01L29/749
摘要： An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.
摘要翻译：提供了一种绝缘栅极晶闸管，其包括：第一导电型基极层，形成在基极层中的第一和第二导电型基极区域，形成在第一基极区域中的第一导电型源极区域，形成在第二基极区域中的导电型发射极区域和形成在第一基极区域上的栅极绝缘膜上的栅电极层，第一导电型基极层和第二基极区域，导电型源极区域和第一导电型发射极区域。晶闸管还包括与第一基极区域和第一导电型源极区域接触的第一主电极，形成在第一导电型基极层的另一个表面上的第二导电型发射极层，与第二导电型发射极层接触的第二主电极，连接到栅电极层的栅电极; 以及覆盖所述第二第二导电型基极区域和所述第一导电型发射极区域的整个表面区域的绝缘膜。在该绝缘栅极晶闸管中，介于第一导电型基极层和第一导电型源极区域之间的第一第二导电型基极区域的露出面部分的宽度比露出面部分位于第一导电型基极层和第一导电型发射极区域之间的第二第二导电型基极区域。

4. 发明授权

US6091087A Insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管
公开(公告)号：US6091087A
公开(公告)日：2000-07-18
申请号：US852269
申请日：1997-05-06
申请人： Noriyuki Iwamuro , Yuichi Harada , Tadayoshi Iwaana
发明人： Noriyuki Iwamuro , Yuichi Harada , Tadayoshi Iwaana
IPC分类号： H01L29/745 , H01L29/749 , H01L29/74 , H01L29/00
CPC分类号： H01L29/7455 , H01L29/749
摘要： An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. The thyristor further includes a gate electrode formed through an insulating film on the first second-conductivity-type base region, an exposed portion of the first-conductivity-type base layer and the second second-conductivity-type base region, a first main electrode that contacts both the first second-conductivity-type base layer and first-conductivity-type source region, a second-conductivity-type emitter layer formed on the first-conductivity-type base layer, a second main electrode that contacts the second-conductivity-type emitter layer, and an insulating film covering entire areas of surfaces of the second second-conductivity-type base region and first-conductivity-type emitter region. The second second-conductivity-type base region has a diffusion depth that is greater than a larger one of diffusion depths of the first second-conductivity-type base region and a second-conductivity-type well region included in the first second-conductivity-type base region.
摘要翻译：绝缘栅晶闸管包括第一导电型基极层，其具有形成在第一导电型基极层的表面层中的高电阻率，第一和第二第二导电型基极区域，第一导电型源极形成在第一第二导电型基极区域的表面层中的第一导电型发射极区域和形成在第二第二导电型基极区域的表面层中的第一导电型发射极区域。晶闸管还包括通过第一第二导电型基极区域上的绝缘膜形成的栅电极，第一导电型基极层和第二第二导电型基极区域的露出部分，第一主电极其与第一导电型基极层和第一导电型源极区域接触，形成在第一导电型基极层上的第二导电型发射极层，与第二导电型基极层接触的第二主电极型发射极层和覆盖第二第二导电型基极区域和第一导电型发射极区域的整个表面的绝缘膜。所述第二第二导电型基区具有比所述第一第二导电型基区的扩散深度大的扩散深度和包含在所述第一第二导电型基极区中的第二导电型阱区的扩散深度。型基地区。

5. 发明授权

US6054728A Insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管
公开(公告)号：US6054728A
公开(公告)日：2000-04-25
申请号：US54946
申请日：1998-04-03
申请人： Yuichi Harada , Noriyuki Iwamuro , Tadayoshi Iwaana
发明人： Yuichi Harada , Noriyuki Iwamuro , Tadayoshi Iwaana
IPC分类号： H01L29/74 , H01L29/06 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L29/0692 , H01L29/7455 , H01L29/749
摘要： An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.
摘要翻译：提供了一种绝缘栅晶闸管，其包括：第一导电型基极层，形成在基极层中的第一和第二第二导电型基极区域，形成在第一基极区域中的第一导电型源极区域，形成在第二基极区域中的第一导电型发射极区域和形成在第一基极区域上的栅极绝缘膜上的栅极电极层，第一导电型基极层和第二基极区域，导电型源极区域和第一导电型发射极区域。晶闸管还包括与第一基极区域和第一导电型源极区域接触的第一主电极，形成在第一导电型基极层的另一个表面上的第二导电型发射极层，与第二导电型发射极层接触的第二主电极，连接到栅电极层的栅电极; 以及覆盖所述第二第二导电型基极区域和所述第一导电型发射极区域的整个表面区域的绝缘膜。在该绝缘栅极晶闸管中，介于第一导电型基极层和第一导电型源极区域之间的第一第二导电型基极区域的露出面部分的宽度比露出面部分位于第一导电型基极层和第一导电型发射极区域之间的第二第二导电型基极区域。

6. 发明授权

US5991532A Method and apparatus for converting multimegabit-rate data into asynchronous transfer mode cells and vice versa 失效
标题翻译：将多比特率数据转换成异步传输模式单元的方法和装置，反之亦然
公开(公告)号：US5991532A
公开(公告)日：1999-11-23
申请号：US593918
申请日：1996-01-30
申请人： Yuichi Harada
发明人： Yuichi Harada
IPC分类号： H04L29/02 , G06F9/455 , H04L12/28 , H04Q3/00
CPC分类号： H04L12/5601 , H04L2012/5665
摘要： A method that converts multimegabit-rate data into asynchronous transfer mode ATM cells and vice versa which are utilized in a switching system. The method includes determining whether the data is effective or ineffective in accordance with a portion of the data. Converting the data into the ATM cells when the data is determined to be effective. Disregarding the data when the data is determined to be ineffective. The method can be realized by an ATM interface converting unit connected with the switching system and a service interface unit. The service interface unit includes at least one of a switched multimegabit data services interface unit, a frame relay interface unit or a digital signal interface unit.
摘要翻译：一种将多比特率数据转换为异步传输模式ATM信元的方法，反之亦然，在交换系统中被使用。该方法包括根据数据的一部分确定数据是有效还是无效。当数据被确定为有效时，将数据转换成ATM信元。当数据被确定为无效时忽略数据。该方法可以通过与交换系统连接的ATM接口转换单元和服务接口单元来实现。服务接口单元包括交换多千兆位数据业务接口单元，帧中继接口单元或数字信号接口单元中的至少一个。

7. 发明授权

US5006003A Typewriter 失效
标题翻译：打字机
公开(公告)号：US5006003A
公开(公告)日：1991-04-09
申请号：US393810
申请日：1989-08-15
申请人： Yuichi Harada
发明人： Yuichi Harada
IPC分类号： B41J35/14 , B41J35/22
CPC分类号： B41J35/22
摘要： Disclosed is a typewriter wherein a ribbon holder mounted on a carriage movable along a platen holds both a print ribbon and a correction ribbon thereon and is displaceable between its first lift position for facing the print ribbon to a print point on the platen and its second lift position for facing the correction ribbon to said print point.The disclosed typewriter is provided with lift means for displacing the ribbon holder between its first and second lift position, detecting means for detecting the lift position of the ribbon holder, and control means for controlling the lift means to displace the ribbon holder in response to the result of detection of the detecting means, thereby the possibility of errorneous initial printing is eliminated, which may occur when a power supply is once turned off during a correcting action with a correction ribbon and then is turned on again to perform a normal print operation.

8. 发明授权

US4871274A Typewriter 失效
标题翻译：打字机
公开(公告)号：US4871274A
公开(公告)日：1989-10-03
申请号：US137767
申请日：1987-12-24
申请人： Yuichi Harada
发明人： Yuichi Harada
IPC分类号： B41J35/14 , B41J35/22
CPC分类号： B41J35/22
摘要： Disclosed is a typewriter wherein a ribbon holder mounted on a carriage movable along a platen holds both a print ribbon and a correction ribbon thereon and is displaceable between its first lift position for facing the print ribbon to a print point on the platen and its second lift position for facing the correction ribbon to said print point.The disclosed typewriter is provided with lift means for displacing the ribbon holder between its first and second lift position, detecting means for detecting the lift position of the ribbon holder, and control means for controlling the lift means to displace the ribbon holder in response to the result of detection of the detecting means, thereby the possibility of errorneous initial printing is eliminated, which may occur when a power supply is once turned off during a correcting action with a correction ribbon and then is turned on again to perform a normal print operation.

9. 发明申请

US20070029636A1 Semiconductor Device and Manufacturing Method Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070029636A1
公开(公告)日：2007-02-08
申请号：US11420779
申请日：2006-05-29
申请人： Hiroshi Kanemaru , Naoki Kumagai , Yuichi Harada , Yoshihiro Ikura , Yoshiaki Minoya
发明人： Hiroshi Kanemaru , Naoki Kumagai , Yuichi Harada , Yoshihiro Ikura , Yoshiaki Minoya
IPC分类号： H01L29/00
CPC分类号： H01L21/76283 , H01L21/76275 , H01L21/823878 , H01L21/84 , H01L27/12 , H01L29/78603
摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
摘要翻译：绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达后表面。这消除了表面状态的影响引入到形成在背面的绝缘体膜与n半导体衬底之间的界面中，由此可以获得优异的击穿电压。

10. 发明授权

US5914503A Insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管
公开(公告)号：US5914503A
公开(公告)日：1999-06-22
申请号：US798743
申请日：1997-02-13
申请人： Noriyuki Iwamuro , Yuichi Harada
发明人： Noriyuki Iwamuro , Yuichi Harada
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L29/749 , H01L29/7455
摘要： An insulated gate thyristor is provided in which an inversion layer is created beneath a gate electrode to which a voltage is applied. An emitter region of a first conductivity type is biased to the same potential as a first main electrode via a MOSFET channel, and a thyristor portion consisting of the emitter region, a second base region of a second conductivity type, a base layer of the first conductivity type and an emitter layer of the second conductivity type is turned on. As electrons are injected uniformly from the entire emitter region, the insulated gate thyristor quickly shifts to the thyristor mode, and the on-voltage of the insulated gate thyristor of the invention is lowered. The insulated gate thyristor of the invention does not require a hole current that flows through the second base region of a convention EST in the Z-direction. In turning off, the pn junction recovers quickly without causing current localization, and the breakdown withstand capability if improved.
摘要翻译：提供一种绝缘栅极晶闸管，其中在施加电压的栅电极下面形成反型层。第一导电类型的发射极区域经由MOSFET沟道被偏置到与第一主电极相同的电位，并且由发射极区域，第二导电类型的第二基极区域，第一导电类型的基极层导电类型和第二导电类型的发射极层导通。由于电子从整个发射极区均匀注入，所以绝缘栅极晶闸管迅速转移到晶闸管模式，并且本发明的绝缘栅晶闸管的导通电压降低。本发明的绝缘栅极晶闸管不需要在常规EST的Z方向上流过第二基极区域的空穴电流。在关闭时，pn结快速恢复，而不会导致电流定位，如果改进，击穿耐受能力。

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