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    • 8. 发明授权
    • Tri-level-cell DRAM and sense amplifier with alternating offset voltage
    • 具有交替偏置电压的三电平单元DRAM和读出放大器
    • US09478277B1
    • 2016-10-25
    • US14844003
    • 2015-09-03
    • Bo Liu
    • Bo Liu
    • G11C11/401G11C11/4096G11C11/56
    • G11C11/4096G11C7/02G11C7/065G11C7/08G11C11/4091G11C11/4094G11C11/4099G11C11/565G11C16/10G11C16/30G11C2211/5634
    • Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells. Selected memory cell connected to bitline (BLT) to develop signal voltage, and adjacent reference bitline (BLR) develops reference voltage at VDD/2. An asymmetrical sensing amplifier (ASA), which has alternative positive offset and negative offset, is used to sense signal voltage and reference voltage for both their difference and sameness. ASA control signals, A and B, switch at different timing points or at different voltage level or the combination of both to have offset voltage set at either positive or negative polarity. Two consecutive read out from one ASA or one single read out from two ASA can be implemented to read memory cells data to local IOs. Output from ASA will be used to restore voltage back to the accessed memory cells.
    • 三电平单元动态随机存取存储器(DRAM)将3级电压(0,VDD / 2,VDD)存储到多个存储单元中。 连接到位线(BLT)的选定存储单元产生信号电压,并且相邻的参考位线(BLR)产生VDD / 2的参考电压。 具有替代正偏移和负偏移的不对称感测放大器(ASA)用于检测信号电压和参考电压两者的差异和相同性。 ASA控制信号A和B在不同的定时点或不同的电压电平下进行切换,或者两者的组合使偏移电压设置为正或负极性。 可以实现从一个ASA或两个ASA读取的两个连续读出,以将内存单元数据读取到本地IO。 来自ASA的输出将用于将电压恢复到访问的存储单元。