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1. 发明授权

US06723638B1 Performance in flash memory devices 有权
标题翻译：闪存设备性能
公开(公告)号：US06723638B1
公开(公告)日：2004-04-20
申请号：US10358866
申请日：2003-02-05
申请人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang
发明人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang
IPC分类号： H01L2144
CPC分类号： H01L29/66825 , H01L21/28273
摘要： In a method of fabricating a semiconductor device, a gate oxide layer is provided on a silicon substrate. A first polysilicon layer is provided on the gate oxide layer, a dielectric layer is provided on the first polysilicon layer, and a second polysilicon layer is provided on the dielectric layer. Upon appropriate masking, an etch step is undertaken, etching the second polysilicon layer, dielectric layer, first polysilicon layer, and gate oxide layer to remove portions thereof to expose the silicon substrate and to form a stacked gate structure on the silicon substrate. A rapid thermal anneal is undertaken for a short period of time, i.e., for example 10-20 seconds, to grow a thin oxide layer on the stacked gate structure. Then, another oxide layer is deposited over the oxide layer which was formed by rapid thermal anneal.
摘要翻译：在制造半导体器件的方法中，在硅衬底上设置栅氧化层。在栅极氧化层上设置第一多晶硅层，在第一多晶硅层上设置电介质层，在电介质层上设置第二多晶硅层。在适当的掩蔽下，进行蚀刻步骤，蚀刻第二多晶硅层，电介质层，第一多晶硅层和栅极氧化物层以去除其部分以暴露硅衬底并在硅衬底上形成堆叠的栅极结构。在短时间内（即例如10-20秒）进行快速热退火以在堆叠的栅极结构上生长薄的氧化物层。然后，在通过快速热退火形成的氧化物层上沉积另一氧化物层。

2. 发明授权

US06953752B1 Reduced silicon gouging and common source line resistance in semiconductor devices 失效
标题翻译：在半导体器件中减少硅沟槽和普通源极线电阻
公开(公告)号：US06953752B1
公开(公告)日：2005-10-11
申请号：US10358756
申请日：2003-02-05
申请人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
发明人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
IPC分类号： H01L21/311 , H01L21/8247
CPC分类号： H01L27/11521
摘要： In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.
摘要翻译：在进行半导体结构的自对准源蚀刻的本方法中，衬底在其上具有氧化物。第一和第二相邻的堆叠栅极结构设置在基板上。在第一和第二栅极堆叠结构的相应的第一和第二相邻侧上设置氧化物间隔物，并且在各个氧化物间隔物上设置多晶硅间隔物。使用栅极结构，氧化物间隔物和多晶硅间隔物作为掩模进行自对准源蚀刻。然后去除多晶硅间隔物，并且使用氧化物间隔物作为掩模在衬底上提供金属（例如钴）。进行硅化步骤以在衬底上形成金属硅化物共同源极线。

3. 发明授权

US06867119B2 Nitrogen oxidation to reduce encroachment 有权
标题翻译：氮氧化减少侵蚀
公开(公告)号：US06867119B2
公开(公告)日：2005-03-15
申请号：US10284866
申请日：2002-10-30
申请人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
发明人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66825 , H01L21/28247 , H01L21/28273
摘要： A method of manufacturing a metal oxide semiconductor. A gate structure of the metal oxide semiconductor is etched. A nitrogen-comprising gas, which may be NO or N2O, is made to flow over the metal oxide semiconductor. A pre-implant film is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects. In this novel manner, gate stack edge defects may be physically repaired without deleterious consequences to the electrical behavior of a metal oxide semiconductor device. The novel application of silicon nitride to this application allows thin repair layers to be grown. Advantageously, semiconductors manufactured using embodiments of the present invention may utilize smaller process feature sizes, resulting in denser arrays of semiconductor devices, resulting in lower costs for such devices and realizing a competitive advantage to practitioners of the improvements in the arts herein described.
摘要翻译：一种制造金属氧化物半导体的方法。蚀刻金属氧化物半导体的栅极结构。使含氮气体（可以是NO或N 2 O）流过金属氧化物半导体。在门结构的边缘上生长预植入膜。预植入膜可以修复由蚀刻工艺引起的栅堆叠边缘的损坏。该膜可以基本上是氮化硅。有利地，这种膜可以比常规二氧化硅膜薄。更薄的膜对隧道氧化物中的不均匀性没有有害的贡献。不均匀隧道氧化物可能导致栅极和沟道之间的不均匀场。非均匀场可能有许多有害影响。有利地，本发明的实施例克服了修复栅极堆叠边缘缺陷的现有技术缺陷。以这种新颖的方式，可以物理地修复栅极堆叠边缘缺陷，而不会对金属氧化物半导体器件的电气行为产生有害影响。氮化硅在该应用中的新颖应用允许生长薄的修复层。有利地，使用本发明的实施例制造的半导体可以利用较小的工艺特征尺寸，导致更密集的半导体器件阵列，从而导致这些器件的成本降低，并且对于本领域技术人员的改进实现了竞争优势。

4. 发明授权

US06700201B1 Reduction of sector connecting line capacitance using staggered metal lines 有权
标题翻译：使用交错金属线路减少扇区连接线路电容
公开(公告)号：US06700201B1
公开(公告)日：2004-03-02
申请号：US10013902
申请日：2001-12-11
申请人： Richard Fastow , Yue-Song He , Sameer Haddad
发明人： Richard Fastow , Yue-Song He , Sameer Haddad
IPC分类号： H01L2348
CPC分类号： H01L27/105 , Y10S257/906
摘要： In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines. The sector connecting lines include a first set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across the sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., the sector connecting lines are in a staggered relation.
摘要翻译：在存储器阵列中，包括多个扇区。每个扇区包括位于平面中的多个并行位线。扇区连接线连接扇区。这些扇形连接线彼此平行并且与位线平行。扇形连接线包括第一组扇形连接线，它们位于与位线的平面平行且相邻并与其间隔开的平面中;以及第二组扇形连接线，其位于平行于并相邻并间隔开的平面中从第一套扇形连接线的平面。当跨扇区观看时，连续的扇区连接线以交替方式位于其两个不同的平面中，即扇区连接线处于交错关系。

5. 发明授权

US07816726B2 Nonvolatile memories with laterally recessed charge-trapping dielectric 有权
标题翻译：具有横向凹陷的电荷俘获电介质的非易失性存储器
公开(公告)号：US07816726B2
公开(公告)日：2010-10-19
申请号：US11961183
申请日：2007-12-20
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42344
摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.
摘要翻译：非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

6. 发明申请

US20090184359A1 Split-gate non-volatile memory devices having nitride tunneling layers 审中-公开
标题翻译：具有氮化物隧穿层的分离栅非易失性存储器件
公开(公告)号：US20090184359A1
公开(公告)日：2009-07-23
申请号：US12017961
申请日：2008-01-22
申请人： Yue-Song He , Len Mei
发明人： Yue-Song He , Len Mei
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/42344
摘要： A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.
摘要翻译：具有与单元堆叠相邻形成的单元堆叠和选择栅极的存储器件。电池堆包括形成在衬底的沟道区上的第一无陷波氮化物层，形成在第一氮化物层上的第二氮化物层，形成在第二氮化物层上的氧化物层， K氧化物层和作为选择栅极的多隔板作为与控制栅极相邻形成。

7. 发明授权

US07079424B1 Methods and systems for reducing erase times in flash memory devices 有权
标题翻译：用于减少闪存设备中擦除时间的方法和系统
公开(公告)号：US07079424B1
公开(公告)日：2006-07-18
申请号：US10945914
申请日：2004-09-22
申请人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
发明人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
IPC分类号： G11C11/34
CPC分类号： G11C16/107 , G11C16/16 , G11C16/3468
摘要： A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.
摘要翻译：提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程到第一预定水平。可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

8. 发明授权

US06898124B1 Efficient and accurate sensing circuit and technique for low voltage flash memory devices 有权
标题翻译：高效，准确的低压闪存器件感测电路和技术
公开(公告)号：US06898124B1
公开(公告)日：2005-05-24
申请号：US10678446
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C11/56 , G11C16/06 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
摘要翻译：示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。感测电路还包括连接到第一晶体管的去耦电路。解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

9. 发明授权

US06833297B1 Method for reducing drain induced barrier lowering in a memory device 有权
标题翻译：用于减少存储器件中的漏极引起的屏障降低的方法
公开(公告)号：US06833297B1
公开(公告)日：2004-12-21
申请号：US10265001
申请日：2002-10-04
申请人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
发明人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
IPC分类号： H01L218234
CPC分类号： H01L29/66825 , H01L29/7883
摘要： The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.
摘要翻译：本发明是一种用于制造存储器件的方法。在一个实施例中，第一杂质浓度沉积在存储器件的沟道区中。然后在通道区域中产生第二杂质浓度，其覆盖第一杂质浓度。最后，在通道区域上制造存储器阵列。存储器阵列覆盖第一杂质浓度和第二杂质浓度。

10. 发明授权

US06177316B1 Post barrier metal contact implantation to minimize out diffusion for NAND device 有权
标题翻译：后阻挡金属接触植入，以最小化NAND器件的扩散
公开(公告)号：US06177316B1
公开(公告)日：2001-01-23
申请号：US09412278
申请日：1999-10-05
申请人： Yue-Song He , Kent K. Chang , John J. Wang
发明人： Yue-Song He , Kent K. Chang , John J. Wang
IPC分类号： H01L21336
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a NAND-type memory cell structure. The present invention forgoes providing a contact mask implantation process prior to deposition of a metal barrier layer, which is a typical order of processing the NAND-type memory cell. Instead, in the present invention, the metal barrier layer is deposited on a core area of the NAND-type memory cell prior to contact mask implantation. Thereafter, the contact mask implantation process is performed on the structure in a conventional manner.
摘要翻译：一种用于制造NAND型存储单元结构的改进方法。本发明放弃在沉积金属阻挡层之前提供接触掩模注入工艺，这是处理NAND型存储单元的典型顺序。相反，在本发明中，在接触掩模植入之前，将金属阻挡层沉积在NAND型存储单元的核心区域上。此后，以常规方式对结构进行接触掩模注入工艺。

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