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    • 1. 发明申请
    • Program methods for split-gate memory
    • 分闸存储器的编程方法
    • US20080068887A1
    • 2008-03-20
    • US11524128
    • 2006-09-20
    • Yue-Der ChihShih-Wei WangDerek Lin
    • Yue-Der ChihShih-Wei WangDerek Lin
    • G11C16/04G11C11/34G11C16/06
    • G11C16/0425G11C16/3418G11C16/3427
    • An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.
    • 闪存单元阵列包括包括多行的第一扇区,其中每行连接到控制栅极线,第一行包括第一扇区中的第一闪存单元,第一控制栅极线连接控制栅极线, 第一行中的闪存单元的栅极,第一扇区中的第二行,并且包括与第一闪存单元共享公共源极线和相同位线的第二闪存单元;连接第二控制栅极线的第二控制栅极线 第二行中存储单元的控制栅极,其中第一和第二控制栅极线彼此断开,第二扇区包括多行,其中每行连接到控制栅极线,正高 电压(HV)驱动器,连接到第一扇区中的第一控制栅极线和第二扇区中的控制栅极线。
    • 2. 发明授权
    • Program methods for split-gate memory
    • 分闸存储器的编程方法
    • US07495960B2
    • 2009-02-24
    • US11524128
    • 2006-09-20
    • Yue-Der ChihShih-Wei WangDerek Lin
    • Yue-Der ChihShih-Wei WangDerek Lin
    • G11C16/04
    • G11C16/0425G11C16/3418G11C16/3427
    • An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.
    • 闪存单元阵列包括包括多行的第一扇区,其中每行连接到控制栅极线,第一行包括第一扇区中的第一闪存单元,第一控制栅极线连接控制栅极线, 第一行中的闪存单元的栅极,第一扇区中的第二行,并且包括与第一闪存单元共享公共源极线和相同位线的第二闪存单元;连接第二控制栅极线的第二控制栅极线 第二行中存储单元的控制栅极,其中第一和第二控制栅极线彼此断开,第二扇区包括多行,其中每行连接到控制栅极线,正高 电压(HV)驱动器,连接到第一扇区中的第一控制栅极线和第二扇区中的控制栅极线。
    • 5. 发明授权
    • Access control via organization charts
    • 通过组织图进行访问控制
    • US08479302B1
    • 2013-07-02
    • US13036174
    • 2011-02-28
    • Derek Lin
    • Derek Lin
    • G06F21/00
    • G06F21/62
    • Improved techniques involve controlling access to data based on who has previously accessed the data. For example, when a user submits a request to access a resource, a list of those users who have accessed the resource is generated. Identifiers associated with the requesting user and the accessing users from the list of users are located within an organization chart which contains information about the hierarchal level and department to which users within the organization belong. As an example, if the requesting user is an executive-level employee and the accessing users are also executive-level users, then access to the resource is granted. If, on the other hand, the requesting user is on the level of an individual contributor, or a contractor, then access to the resource is denied. Further, access requests can be recorded in the access log for tracking.
    • 改进的技术涉及根据谁先前访问过数据来控制对数据的访问。 例如,当用户提交访问资源的请求时,生成访问资源的那些用户的列表。 与请求用户相关联的标识符和来自用户列表的访问用户位于组织图中,该组织图包含有关组织中的用户所属的层级级别和部门的信息。 作为示例,如果请求用户是执行级员工,并且访问用户也是执行级用户,则授予对资源的访问。 另一方面,如果请求用户处于单独贡献者或承包商的级别,则拒绝对资源的访问。 此外,访问请求可以记录在访问日志中以进行跟踪。
    • 7. 发明授权
    • Click stream analysis for fraud detection
    • 点击流分析进行欺诈检测
    • US08880441B1
    • 2014-11-04
    • US13433633
    • 2012-03-29
    • Jidong ChenDerek LinAlon KaufmanYael Villa
    • Jidong ChenDerek LinAlon KaufmanYael Villa
    • G06F15/18
    • G06F15/18G06F21/316
    • An improved technique trains a fraud detection system to use mouse movement data as part of a user profile. Along these lines, a training apparatus receives sets of mouse movement datasets generated by a legitimate user and/or a fraudulent user. The training apparatus assigns each mouse movement dataset to a cluster according to one of several combinations of representations, distance metrics, and cluster metrics. By correlating the clusters with the origins of the mouse movement datasets (legitimate or fraudulent user), the training apparatus constructs a robust framework for detecting fraud at least partially based on mouse movement data.
    • 改进的技术训练欺诈检测系统,以使用鼠标移动数据作为用户简档的一部分。 沿着这些线路,训练装置接收由合法用户和/或欺诈用户生成的一组鼠标移动数据集。 训练装置根据表示,距离度量和簇度量的若干组合之一将每个鼠标移动数据集分配给群集。 通过将群集与鼠标移动数据集(合法或欺诈用户)的起源相关联,训练装置至少部分地基于鼠标移动数据构建用于检测欺诈的鲁棒框架。
    • 8. 发明申请
    • Logic compatible storage device
    • 逻辑兼容存储设备
    • US20080006868A1
    • 2008-01-10
    • US11483916
    • 2006-07-10
    • Te-Hsun HsuYung-Tao LinDerek LinJack Yeh
    • Te-Hsun HsuYung-Tao LinDerek LinJack Yeh
    • H01L29/76
    • H01L27/115G11C16/0433H01L27/11521H01L27/11558
    • A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.
    • 提供了一种非易失性存储单元及其制造方法。 非易失性存储单元包括在半导体衬底上的浮动栅极,包括第一板,浮栅及其之间的电介质的第一电容器,包括第二板,浮栅及其之间的电介质的第二电容器, 第三电容器,包括连接到浮置栅极的第三板和第四板,其中第三板和第四板形成在半导体衬底上的金属化层中。 第一电容器的第一板包括在半导体衬底中的第一掺杂区和第二掺杂区。 非易失性存储单元还包括晶体管,其包括在半导体衬底上的栅电极,其中晶体管的源/漏区连接到第一电容器的第一掺杂区。