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1. 发明申请

US20130141149A1 APPARATUS AND METHOD FOR DUTY CYCLE CALIBRATION 有权
标题翻译：用于周期校准的装置和方法
公开(公告)号：US20130141149A1
公开(公告)日：2013-06-06
申请号：US13612729
申请日：2012-09-12
申请人： Yu-Li HSUEH , Chih-Hsien SHEN , Jing-Hong Conan ZHAN
发明人： Yu-Li HSUEH , Chih-Hsien SHEN , Jing-Hong Conan ZHAN
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.
摘要翻译：用于占空比校准的装置包括输入校准电路，延迟链，第一比较器和第二比较器。输入校准电路根据第一控制信号校准输入时钟信号，以产生输入校准时钟信号。延迟链包括串联耦合的多个延迟单元，并延迟输入校准时钟信号，以产生第一延迟时钟信号和第二延迟时钟信号。延迟单元中的至少两个具有根据第二控制信号来控制的可调延迟时间。第一比较器将输入校准时钟信号与第一延迟时钟信号进行比较，以产生第一控制信号。第二比较器将输入校准时钟信号与第二延迟时钟信号进行比较，以产生第二控制信号。

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