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1. 发明授权

US08124494B2 Method for reshaping silicon surfaces with shallow trench isolation 有权
标题翻译：用浅沟槽隔离重新形成硅表面的方法
公开(公告)号：US08124494B2
公开(公告)日：2012-02-28
申请号：US11778558
申请日：2007-07-16
申请人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
发明人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
IPC分类号： H01L21/76
CPC分类号： H01L29/7833 , H01L21/76224
摘要： A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.
摘要翻译：提出了一种通过用牺牲层重塑硅表面来制造半导体器件的方法。在本发明中，形成牺牲电介质层和去除牺牲电介质层的步骤被重复多次，以便从场氧化物附近的硅表面去除尖锐的边缘。本发明的另一方面包括制造一种MOSFET晶体管，其将多个牺牲层的形成和去除结合到该工艺中。

2. 发明授权

US08253206B2 Method for reshaping silicon surfaces with shallow trench isolation 有权
公开(公告)号：US08253206B2
公开(公告)日：2012-08-28
申请号：US13221654
申请日：2011-08-30
申请人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
发明人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
IPC分类号： H01L21/70
CPC分类号： H01L29/7833 , H01L21/76224
摘要： A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.

3. 发明申请

US20110309417A1 Method for Reshaping Silicon Surfaces with Shallow Trench Isolation 有权
标题翻译：用浅沟槽隔离重新成形硅表面的方法
公开(公告)号：US20110309417A1
公开(公告)日：2011-12-22
申请号：US13221654
申请日：2011-08-30
申请人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
发明人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7833 , H01L21/76224
摘要： A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.
摘要翻译：提出了一种通过用牺牲层重塑硅表面来制造半导体器件的方法。在本发明中，形成牺牲电介质层和去除牺牲电介质层的步骤被重复多次，以便从场氧化物附近的硅表面去除尖锐的边缘。本发明的另一方面包括制造一种MOSFET晶体管，其将多个牺牲层的形成和去除结合到该工艺中。

4. 发明申请

US20090023255A1 Method for Reshaping Silicon Surfaces with Shallow Trench Isolation 有权
标题翻译：用浅沟槽隔离重新成形硅表面的方法
公开(公告)号：US20090023255A1
公开(公告)日：2009-01-22
申请号：US11778558
申请日：2007-07-16
申请人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
发明人： Yu-Hsiung Wang , Wen-Ting Chu , Eric Chen , Hsien-Wei Chin
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/76224
摘要： A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.
摘要翻译：提出了一种通过用牺牲层重塑硅表面来制造半导体器件的方法。在本发明中，形成牺牲电介质层和去除牺牲电介质层的步骤被重复多次，以便从场氧化物附近的硅表面去除尖锐的边缘。本发明的另一方面包括制造一种MOSFET晶体管，其将多个牺牲层的形成和去除结合到该工艺中。

5. 发明授权

US08896096B2 Process-compatible decoupling capacitor and method for making the same 有权
标题翻译：过程兼容去耦电容及其制作方法
公开(公告)号：US08896096B2
公开(公告)日：2014-11-25
申请号：US13553086
申请日：2012-07-19
申请人： Kuo-Chi Tu , Wen-Ting Chu
发明人： Kuo-Chi Tu , Wen-Ting Chu
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L28/40 , H01L29/94 , H01L45/04 , H01L2924/0002 , H01L2924/00
摘要： Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.
摘要翻译：提供去耦电容器件。去耦电容器装置包括在沉积工艺中沉积的第一电介质层部分，其沉积用于非易失性存储单元的第二电介质层部分。使用单个掩模对两个部分进行图案化。还提供了片上系统（SOC）器件，SOC包括位于单个金属间介电层中的RRAM单元和去耦电容器。还提供了一种形成工艺兼容去耦电容器的方法。该方法包括图案化顶部电极层，绝缘层和底部电极层，以形成非易失性存储元件和去耦电容器。

6. 发明授权

US07227218B2 Method and system for forming source regions in memory devices 有权
标题翻译：用于在存储器件中形成源区的方法和系统
公开(公告)号：US07227218B2
公开(公告)日：2007-06-05
申请号：US11094035
申请日：2005-03-30
申请人： Yi-Shing Chang , Wen-Ting Chu
发明人： Yi-Shing Chang , Wen-Ting Chu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
摘要翻译：公开了一种存储器件及其制造方法。该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。此外，控制门材料填充在第三开口中。

7. 发明申请

US20070120172A1 Logic compatible non-volatile memory cell 有权
标题翻译：逻辑兼容的非易失性存储单元
公开(公告)号：US20070120172A1
公开(公告)日：2007-05-31
申请号：US11248357
申请日：2005-10-12
申请人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
发明人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
摘要翻译：提供了一种非易失性存储单元及其制造方法。非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。非易失性存储单元还包括与第一电容器串联连接的晶体管。晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

8. 发明申请

US20060163686A1 Novel process to improve programming of memory cells 有权
标题翻译：改进存储单元编程的新过程
公开(公告)号：US20060163686A1
公开(公告)日：2006-07-27
申请号：US11044813
申请日：2005-01-26
申请人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
发明人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/10894 , H01L27/11
摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.
摘要翻译：提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。该方法包括以下步骤：形成覆盖在半导体衬底的表面上的底部抗反射涂层（BARC）层和STI结构的表面; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

9. 发明申请

US20060046403A1 Method of forming separated charge-holding regions in a semiconductor device 审中-公开
标题翻译：在半导体器件中形成分离的电荷保持区域的方法
公开(公告)号：US20060046403A1
公开(公告)日：2006-03-02
申请号：US10931547
申请日：2004-08-31
申请人： Wen-Ting Chu , Chia-Ta Hsieh , Hung-Cheng Sung
发明人： Wen-Ting Chu , Chia-Ta Hsieh , Hung-Cheng Sung
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/512 , H01L21/28202 , H01L29/40117 , H01L29/518 , H01L29/66833
摘要： A method of forming a semiconductor device comprises forming a gate dielectric layer and a gate electrode over the gate dielectric layer on a semiconductor substrate, partially removing the gate dielectric layer to form two recesses separated by the gate dielectric layer and disposed substantially under the gate electrode, and substantially filling the two recesses with an oxide layer and a material layer to form two separated regions operable to each hold an electrical charge.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上的栅介电层上形成栅极电介质层和栅电极，部分地去除栅极电介质层以形成由栅极电介质层分开并设置在栅电极下方的两个凹槽并且用氧化物层和材料层基本上填充两个凹部以形成可操作以保持电荷的两个分离的区域。

10. 发明授权

US06902978B2 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
标题翻译：在分闸器快闪EEPROM单元中制作选择栅极的方法及其结构
公开(公告)号：US06902978B2
公开(公告)日：2005-06-07
申请号：US10929396
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

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