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1. 发明授权

US08028189B2 Recoverable machine check handling 失效
标题翻译：可回收机检查处理
公开(公告)号：US08028189B2
公开(公告)日：2011-09-27
申请号：US10991207
申请日：2004-11-17
申请人： Yu-Cheng Hsu , John N. McCauley , Juan J. Ruiz , William G. Sherman , Cheng-Chung Song
发明人： Yu-Cheng Hsu , John N. McCauley , Juan J. Ruiz , William G. Sherman , Cheng-Chung Song
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/079
摘要： A technique for handling hardware errors in a computing system, such as a data storage facility, while avoiding a system crash. An interface is registered with an operating system of the computing system to process hardware errors. When a hardware error is detected, the interface checks an error register to identify the adapter that likely causes the error, and quarantines, e.g., blocks off, the offending adapter from the computing system. The interface then notifies the operating system that the error has been handled, thereby causing the operating system to bypass a system crash that would otherwise occur. The interface can be provided as a kernel extension of a device driver associated with the operating system.
摘要翻译：一种用于处理诸如数据存储设备的计算系统中的硬件错误的技术，同时避免系统崩溃。在计算系统的操作系统上注册一个接口来处理硬件错误。当检测到硬件错误时，接口检查错误寄存器以识别可能导致错误的适配器，并将违规适配器从计算系统隔离，例如阻止。接口然后通知操作系统该错误已被处理，从而导致操作系统绕过否则将发生的系统崩溃。该接口可以作为与操作系统相关联的设备驱动程序的内核扩展来提供。

2. 发明授权

US07650467B2 Coordination of multiprocessor operations with shared resources 失效
标题翻译：多处理器操作与共享资源协调
公开(公告)号：US07650467B2
公开(公告)日：2010-01-19
申请号：US12052569
申请日：2008-03-20
申请人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
发明人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

3. 发明申请

US20060117147A1 Managing multiprocessor operations 失效
标题翻译：管理多处理器操作
公开(公告)号：US20060117147A1
公开(公告)日：2006-06-01
申请号：US11001476
申请日：2004-11-30
申请人： Stephen Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Rankin , Cheng-Chung Song
发明人： Stephen Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Rankin , Cheng-Chung Song
IPC分类号： G06F12/14
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

4. 发明授权

US08375180B2 Storage application performance matching 有权
标题翻译：存储应用性能匹配
公开(公告)号：US08375180B2
公开(公告)日：2013-02-12
申请号：US12700964
申请日：2010-02-05
申请人： Lawrence Y. Chiu , Clement L. Dickey , Yu-Cheng Hsu , Joseph S. Hyde, II , Paul H. Muench , Cheng-Chung Song
发明人： Lawrence Y. Chiu , Clement L. Dickey , Yu-Cheng Hsu , Joseph S. Hyde, II , Paul H. Muench , Cheng-Chung Song
IPC分类号： G06F12/00
CPC分类号： G06F3/0647 , G06F3/0617 , G06F3/0685
摘要： Input/output (I/O) activity in the multiple tier storage system is monitored to collect statistical information. The statistical information is recurrently transformed into an exponential moving average (EMA) of the I/O activity having a predefined smoothing factor. Data portions in the multiple tier storage system are sorted into buckets of varying temperatures corresponding to the EMA. At least one data migration plan is recurrently generated for matching the sorted data portions to at least one of an available plurality of storage device classes. One data portion sorted into a higher temperature bucket is matched with a higher performance storage device class of the available plurality of storage device classes than another data portion sorted into a lower temperature bucket.
摘要翻译：监控多层存储系统中的输入/输出（I / O）活动以收集统计信息。统计信息被循序变换成具有预定平滑因子的I / O活动的指数移动平均（EMA）。将多层存储系统中的数据部分分类为对应于EMA的不同温度的桶。循环地生成至少一个数据迁移计划，用于将排序的数据部分与可用的多个存储设备类中的至少一个进行匹配。分类到较高温度桶中的一个数据部分与可分解为较低温度桶的另一数据部分的可用多个存储设备类别的更高性能的存储设备类相匹配。

5. 发明授权

US08255627B2 Secondary cache for write accumulation and coalescing 有权
标题翻译：二级缓存用于写入累积和合并
公开(公告)号：US08255627B2
公开(公告)日：2012-08-28
申请号：US12577164
申请日：2009-10-10
申请人： Stephen LaRoux Blinick , Cheng-Chung Song , Lokesh Mohan Gupta , Yu-Cheng Hsu
发明人： Stephen LaRoux Blinick , Cheng-Chung Song , Lokesh Mohan Gupta , Yu-Cheng Hsu
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1008 , G06F11/1076 , G06F12/0866
摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.
摘要翻译：本文公开了一种高效地使用大型二级高速缓存的方法。在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。这些数据轨道可以包括经修改的数据和/或未修改的数据。该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。本文还公开并要求相应的计算机程序产品和装置。

6. 发明申请

US20120191904A1 SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
标题翻译：用于写入累积和分析的二次高速缓存
公开(公告)号：US20120191904A1
公开(公告)日：2012-07-26
申请号：US13430613
申请日：2012-03-26
申请人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
发明人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0804 , G06F11/1008 , G06F11/1076 , G06F12/0866
摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.
摘要翻译：本文公开了一种高效地使用大型二级高速缓存的方法。在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。这些数据轨道可以包括经修改的数据和/或未修改的数据。该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。本文还公开了相应的计算机程序产品和装置。

7. 发明授权

US07774656B2 System and article of manufacture for handling a fabric failure 失效
标题翻译：用于处理织物失效的系统和制品
公开(公告)号：US07774656B2
公开(公告)日：2010-08-10
申请号：US12350189
申请日：2009-01-07
申请人： Yu-Cheng Hsu , John Norbert McCauley , William Griswold Sherman , Cheng-Chung Song
发明人： Yu-Cheng Hsu , John Norbert McCauley , William Griswold Sherman , Cheng-Chung Song
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0745
摘要： Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.
摘要翻译：提供了一种用于处理织物故障的方法，系统和程序。模块拦截指示在提供到共享设备的连接的结构中的路径的故障的信号。该模块在操作系统中为设备驱动程序产生中断，为操作系统提供由于路径故障而无法访问的共享设备的接口。设备驱动程序从由于路径故障而无法访问的多个设备的状态从模块请求信息，并且接收指示不可访问设备的信息。设备驱动程序重新配置以停止使用不可访问的设备。

8. 发明授权

US07584271B2 Method, system, and computer readable medium for delaying the configuration of a shared resource 失效
标题翻译：方法，系统和计算机可读介质，用于延迟共享资源的配置
公开(公告)号：US07584271B2
公开(公告)日：2009-09-01
申请号：US10752632
申请日：2004-01-07
申请人： Yu-Cheng Hsu , John Norbert McCauley , Cheng-Chung Song , William Griswold Sherman
发明人： Yu-Cheng Hsu , John Norbert McCauley , Cheng-Chung Song , William Griswold Sherman
IPC分类号： G06F15/177
CPC分类号： G06F9/526 , H04L67/10 , H04L67/34 , H04L69/40
摘要： A determination is made as to whether a configuration indicator associated with a resource indicates a delayed configuration of the resource, wherein the resource is shared by a plurality of processing complexes via a bus, and wherein if the delayed configuration of the resource is indicated then the resource is prevented from being configured during initial program loads of the plurality of processing complexes. The resource is configured by only one of the of plurality of processing complexes that shares the resource, in response to determining that the configuration indicator associated with the resource indicates the delayed configuration of the resource.
摘要翻译：确定与资源相关联的配置指示符是否指示资源的延迟配置，其中经由总线由多个处理复合体共享资源，并且其中如果指示资源的延迟配置，则防止在多个处理复合体的初始程序加载期间配置资源。响应于确定与资源相关联的配置指示符指示资源的延迟配置，资源仅由共享资源的多个处理复合体中的一个配置。

9. 发明授权

US08453157B2 Thread synchronization in simultaneous multi-threaded processor machines 有权
标题翻译：同步多线程处理器机器中的线程同步
公开(公告)号：US08453157B2
公开(公告)日：2013-05-28
申请号：US10990825
申请日：2004-11-16
申请人： Michael Thomas Benhase , Yu-Cheng Hsu , John Norbert McCauley , Louis Alonso Rasor , William Griswold Sherman , Cheng-Chung Song
发明人： Michael Thomas Benhase , Yu-Cheng Hsu , John Norbert McCauley , Louis Alonso Rasor , William Griswold Sherman , Cheng-Chung Song
IPC分类号： G06F9/46
CPC分类号： G06F9/5027 , G06F9/485 , G06F9/5022 , G06F9/52
摘要： Provided are a method, system and article of manufacture, wherein a first application executes at least two threads corresponding to a simultaneous multi-threaded processor whose resources have been acquired by the first application. The at least two threads are synchronized before releasing the simultaneous multi-threaded processor to a second application.
摘要翻译：提供了一种方法，系统和制品，其中第一应用程序执行对应于由第一应用获取其资源的同时多线程处理器的至少两个线程。在将同时多线程处理器释放到第二应用之前，至少两个线程被同步。

10. 发明申请

US20110087837A1 SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
标题翻译：用于写入累积和分析的二次高速缓存
公开(公告)号：US20110087837A1
公开(公告)日：2011-04-14
申请号：US12577164
申请日：2009-10-10
申请人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
发明人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F11/1008 , G06F11/1076 , G06F12/0866
摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.
摘要翻译：本文公开了一种高效地使用大型二级高速缓存的方法。在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。这些数据轨道可以包括经修改的数据和/或未修改的数据。该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。本文还公开并要求对应的计算机程序产品和装置。

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