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1. 发明授权

US07418557B2 Managing multiprocessor operations 失效
标题翻译：管理多处理器操作
公开(公告)号：US07418557B2
公开(公告)日：2008-08-26
申请号：US11001476
申请日：2004-11-30
申请人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
发明人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

2. 发明授权

US07650467B2 Coordination of multiprocessor operations with shared resources 失效
标题翻译：多处理器操作与共享资源协调
公开(公告)号：US07650467B2
公开(公告)日：2010-01-19
申请号：US12052569
申请日：2008-03-20
申请人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
发明人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

3. 发明申请

US20060117147A1 Managing multiprocessor operations 失效
标题翻译：管理多处理器操作
公开(公告)号：US20060117147A1
公开(公告)日：2006-06-01
申请号：US11001476
申请日：2004-11-30
申请人： Stephen Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Rankin , Cheng-Chung Song
发明人： Stephen Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Rankin , Cheng-Chung Song
IPC分类号： G06F12/14
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

4. 发明授权

US07844752B2 Method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions 有权
标题翻译：用于启用多个异步直接存储器访问任务执行的方法，装置和程序存储装置
公开(公告)号：US07844752B2
公开(公告)日：2010-11-30
申请号：US11289908
申请日：2005-11-30
申请人： Lucien Mirabeau , Tiep Quoc Pham
发明人： Lucien Mirabeau , Tiep Quoc Pham
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28
摘要： A method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions. DMA I/O operations and performance are improved by reducing the overhead in DMA chaining events by creating a software DMA queue when a hardware DMA queue overflows and dynamically linking new DMA requests to the software queue until a hardware queue becomes available at which time the software queue is put on the hardware queue. Thus, microcode does not need to manage the hardware queues and keep the DMA engine running continuously because it no longer has to wait for microcode to reset the DMA chain completion indicator.
摘要翻译：一种用于启用多个异步直接存储器访问任务执行的方法，装置和程序存储装置。通过在硬件DMA队列溢出并将新的DMA请求与软件队列动态链接，直到硬件队列变为可用时，通过创建软件DMA队列来减少DMA链接事件的开销来改进DMA I / O操作和性能队列放在硬件队列上。因此，微代码不需要管理硬件队列并保持DMA引擎的连续运行，因为它不再需要等待微代码重置DMA链完成指示器。

5. 发明授权

US07337367B2 Management of memory controller reset 有权
标题翻译：管理存储器控制器复位
公开(公告)号：US07337367B2
公开(公告)日：2008-02-26
申请号：US11030477
申请日：2005-01-06
申请人： Lucien Mirabeau , Charles S Cardinell , Man Wah Ma , Ricardo S Padilla
发明人： Lucien Mirabeau , Charles S Cardinell , Man Wah Ma , Ricardo S Padilla
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0727
摘要： An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.
摘要翻译：提供错误处理方法来处理适配器错误。错误处理例程不是执行中断控制器硬件复位，而是在SDRAM处于自刷新模式并因此不可用时，提供要从高速缓存加载和执行的复位操作的指令。

6. 发明申请

US20070162637A1 Method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions 有权
标题翻译：用于启用多个异步直接存储器访问任务执行的方法，装置和程序存储装置
公开(公告)号：US20070162637A1
公开(公告)日：2007-07-12
申请号：US11289908
申请日：2005-11-30
申请人： Lucien Mirabeau , Tiep Pham
发明人： Lucien Mirabeau , Tiep Pham
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions. DMA I/O operations and performance are improved by reducing the overhead in DMA chaining events by creating a software DMA queue when a hardware DMA queue overflows and dynamically linking new DMA requests to the software queue until a hardware queue becomes available at which time the software queue is put on the hardware queue. Thus, microcode does not need to manage the hardware queues and keep the DMA engine running continuously because it no longer has to wait for microcode to reset the DMA chain completion indicator.
摘要翻译：一种用于启用多个异步直接存储器访问任务执行的方法，装置和程序存储装置。通过在硬件DMA队列溢出并将新的DMA请求与软件队列动态链接，直到硬件队列变为可用时，通过创建软件DMA队列来减少DMA链接事件的开销来改进DMA I / O操作和性能队列放在硬件队列上。因此，微代码不需要管理硬件队列并保持DMA引擎的连续运行，因为它不再需要等待微代码重置DMA链完成指示器。

7. 发明申请

US20060150030A1 Management of memory controller reset 有权
标题翻译：管理存储器控制器复位
公开(公告)号：US20060150030A1
公开(公告)日：2006-07-06
申请号：US11030477
申请日：2005-01-06
申请人： Lucien Mirabeau , Charles Cardinell , Man Ma , Ricardo Padilla
发明人： Lucien Mirabeau , Charles Cardinell , Man Ma , Ricardo Padilla
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0727
摘要： An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.
摘要翻译：提供错误处理方法来处理适配器错误。错误处理例程不是执行中断控制器硬件复位，而是在SDRAM处于自刷新模式并因此不可用时，提供要从高速缓存加载和执行的复位操作的指令。

8. 发明授权

US07469305B2 Handling multiple data transfer requests within a computer system 失效
标题翻译：处理计算机系统内的多个数据传输请求
公开(公告)号：US07469305B2
公开(公告)日：2008-12-23
申请号：US11533587
申请日：2006-09-20
申请人： Lucien Mirabeau , Tiep Q. Pham
发明人： Lucien Mirabeau , Tiep Q. Pham
IPC分类号： G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： In response to multiple data transfer requests from an application, a data definition (DD) chain is generated. The DD chain is divided into multiple DD sub-blocks by determining a bandwidth of channels (BOC) and whether the BOC is less than the DD chain. If so, the DD chain is divided by the available DMA engines. If not, the DD chain is divided by an optimum atomic transfer unit (OATU). If the division yields a remainder, the remainder is added to a last DD sub-block. If the remainder is less than a predetermined value, the size of the last DD sub-block is set to the OATU plus the remainder. Otherwise, the size of the last DD sub-block is set to the remainder. The DD sub-blocks are subsequently loaded into a set of available DMA engines. Each of the available DMA engines performs data transfers on a corresponding DD sub-block until the entire DD chain has been completed.
摘要翻译：响应于来自应用的多个数据传输请求，生成数据定义（DD）链。 DD链通过确定信道带宽（BOC）以及BOC是否小于DD链分为多个DD子块。如果是这样，则DD链由可用的DMA引擎划分。如果不是，DD链被最佳原子转移单位（OATU）除。如果除法产生余数，则余数被添加到最后一个DD子块。如果余数小于预定值，则将最后DD子块的大小设置为OATU加余数。否则，最后一个DD子块的大小设置为余数。 DD子块随后被加载到一组可用的DMA引擎中。每个可用的DMA引擎在相应的DD子块上执行数据传输，直到整个DD链已经完成。

9. 发明申请

US20080168238A1 COORDINATION OF MULTIPROCESSOR OPERATIONS WITH SHARED RESOURCES 失效
标题翻译：使用共享资源协调多个运营商的运营
公开(公告)号：US20080168238A1
公开(公告)日：2008-07-10
申请号：US12052569
申请日：2008-03-20
申请人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
发明人： Stephen LaRoux Blinick , Yu-Cheng Hsu , Lucien Mirabeau , Ricky Dean Rankin , Cheng-Chung Song
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
摘要翻译：在管理多处理器操作时，第一处理器重复地读取高速缓存行，其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。根据高速缓存一致性协议，在共享存储器线和高速缓存线之间保持一致性。在一个方面，重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。在另一方面，在由涉及共享资源的第二处理器完成操作之后，第二处理器将数据写入共享存储器线，以向第一处理器通知第一处理器可以访问共享资源。作为响应，第一处理器根据高速缓存一致性协议改变高速缓存行的状态，并读取由第二处理器写入的数据。描述和要求保护其他实施例。

10. 发明申请

US20080126605A1 Method and Apparatus for Handling Data Transfer Requests Within a Computer System 失效
标题翻译：在计算机系统内处理数据传输请求的方法和装置
公开(公告)号：US20080126605A1
公开(公告)日：2008-05-29
申请号：US11533587
申请日：2006-09-20
申请人： Lucien Mirabeau , Tiep Q. Pham
发明人： Lucien Mirabeau , Tiep Q. Pham
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method for handling multiple data transfer requests from one application within a computer system is disclosed. In response to the receipt of multiple data transfer requests from an application, a data definition (DD) chain is generated for all the data transfer requests. The DD chain is then divided into multiple DD sub-blocks. The DD sub-blocks are subsequently loaded into a set of available direct memory access (DMA) engines. Each of the available DMA engines performs data transfers on a corresponding DD sub-block until the entire DD chain has been completed.
摘要翻译：公开了一种用于处理来自计算机系统内的一个应用的多个数据传送请求的方法。响应于从应用程序接收到多个数据传输请求，为所有数据传输请求生成数据定义（DD）链。然后将DD链分成多个DD子块。 DD子块随后被加载到一组可用的直接存储器访问（DMA）引擎中。每个可用的DMA引擎在相应的DD子块上执行数据传输，直到整个DD链已经完成。

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