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1. 发明授权

US5764959A Adaptive 128-bit floating point load and store instructions for quad-precision compatibility 失效
标题翻译：自适应128位浮点加载和存储指令，用于四精度兼容性
公开(公告)号：US5764959A
公开(公告)日：1998-06-09
申请号：US580069
申请日：1995-12-20
申请人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
发明人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F5/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3013
摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.
摘要翻译：一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。剩余的位位置用0填充。当值移动到存储器时，执行相反的操作。

2. 发明授权

US5729724A Adaptive 128-bit floating point load and store operations for quadruple precision compatibility 失效
标题翻译：自适应128位浮点加载和存储操作，用于四重精度兼容性
公开(公告)号：US5729724A
公开(公告)日：1998-03-17
申请号：US580035
申请日：1995-12-20
申请人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
发明人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
IPC分类号： G06F5/00 , G06F9/302 , G06F9/312 , G06F7/00
CPC分类号： G06F9/30014 , G06F5/00 , G06F9/30036 , G06F9/30043
摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.
摘要翻译：一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。剩余的位位置用0填充。当值移动到存储器时，执行相反的操作。

3. 发明授权

US06378063B2 Method and apparatus for efficiently routing dependent instructions to clustered execution units 有权
标题翻译：用于有效地将依赖指令路由到集群执行单元的方法和装置
公开(公告)号：US06378063B2
公开(公告)日：2002-04-23
申请号：US09220154
申请日：1998-12-23
申请人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
发明人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.
摘要翻译：与链亲和单元和周期内依赖性分析仪组合的分散单元在微处理器中路由指令以提高微处理器性能。分散单元响应于存储在链亲和单元中的信息将指令路由到微处理器中的特定簇。循环内依赖性分析器识别到分散单元的指令组的依赖性，并且分散单元基于这些依赖性来路由组中的指令。

4. 发明授权

US06237077B1 Instruction template for efficient processing clustered branch instructions 失效
标题翻译：用于高效处理集群分支指令的指令模板
公开(公告)号：US06237077B1
公开(公告)日：2001-05-22
申请号：US08949277
申请日：1997-10-13
申请人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
发明人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/3853 , G06F9/3861
摘要： A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.
摘要翻译：提供了一种用于处理指令束中的一个或多个分支指令的方法。指令以捆绑中的执行顺序排序，分支指令在序列中最后排列。捆绑的指令被传送到与捆绑相关联的模板字段指示的执行单元。确定已解决的束的执行序列中的第一个分支指令，并且抑制执行序列中后续指令的退出。

5. 发明授权

US06240510B1 System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions 失效
标题翻译：用于处理指令集的系统，其中指令被发布给具有根据与指令集相关联的模板的优先顺序的执行单元
公开(公告)号：US06240510B1
公开(公告)日：2001-05-29
申请号：US09130387
申请日：1998-08-06
申请人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
发明人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
IPC分类号： G06F915
CPC分类号： G06F9/3885 , G06F9/30094 , G06F9/325 , G06F9/3806 , G06F9/3844
摘要： A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target address, and any side effects. Linking logic receives the resolved branch information and identifies a first branch instruction in execution order for which the branch direction is taken.
摘要翻译：提供一种用于同时处理指令束中的一个或多个分支指令的系统。该系统包括多个分支执行流水线，每个分支执行流水线能够执行分支指令以确定分支方向，目标地址和任何副作用。链接逻辑接收解析的分支信息，并以执行分支方向的执行顺序识别第一分支指令。

6. 发明授权

US06233690B1 Mechanism for saving power on long latency stalls 有权
标题翻译：节省长时间延迟停电的机制
公开(公告)号：US06233690B1
公开(公告)日：2001-05-15
申请号：US09156552
申请日：1998-09-17
申请人： Lynn Choi , Harshvardhan Sharangpani
发明人： Lynn Choi , Harshvardhan Sharangpani
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3225 , G06F1/3237 , G06F1/3287 , G06F9/3824 , G06F9/3838 , G06F9/3857 , Y02D10/128 , Y02D10/171
摘要： A method for gating a clock signal to an execution unit on long latency memory stalls monitors a stall signal, a scoreboard (data) hazard signal, a resource hazard signal, and a data return signal. The clock signal is decoupled from the execution unit when the stall and data hazard signals are asserted for a selected interval and the data return and resource hazard signals are not asserted for a selected interval.
摘要翻译：在长时间延迟存储器停止时，将时钟信号选通到执行单元的方法监视失速信号，记分板（数据）危险信号，资源危险信号和数据返回信号。当停机和数据危险信号被断言一段选定的时间间隔时，时钟信号与执行单元去耦，并且数据返回和资源危险信号在所选时间间隔内不被断言。

7. 发明授权

US06178498B1 Storing predicted branch target address in different storage according to importance hint in branch prediction instruction 失效
标题翻译：根据分支预测指令的重要性提示将预测的分支目标地址存储在不同的存储器中
公开(公告)号：US06178498B1
公开(公告)日：2001-01-23
申请号：US08993450
申请日：1997-12-18
申请人： Harshvardhan Sharangpani , Kent Fielden
发明人： Harshvardhan Sharangpani , Kent Fielden
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/3005 , G06F9/3844 , G06F9/3846
摘要： A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage structures. When the hint information is in a first state, branch prediction information is stored in a first structure that provides single cycle access to the stored information. When the hint information is in a second state, the branch prediction information is stored in a second structure that provides slower access to the stored information.
摘要翻译：提供了一种分支预测指令，其包括用于指示分支预测存储结构的层级中的相关联的分支预测信息的存储位置的提示信息。当提示信息处于第一状态时，分支预测信息被存储在提供对存储的信息的单周期访问的第一结构中。当提示信息处于第二状态时，分支预测信息被存储在提供对存储的信息的较慢访问的第二结构中。

8. 发明授权

US6154760A Instruction to normalize redundantly encoded floating point numbers 失效
标题翻译：对冗余编码的浮点数进行归一化的指令
公开(公告)号：US6154760A
公开(公告)日：2000-11-28
申请号：US562899
申请日：1995-11-27
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F5/01 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.
摘要翻译：本发明是使浮点数归一化的装置。该装置具有包括浮点数的第一存储区域。浮点数包括指数字段和显式位。所述装置还包括当所述显式位未被设置并且所述指数字段具有标识所述浮点数的冗余异常编码的第一预定值时对所述浮点数进行归一化的电路。否则电路的编码不会改变。

9. 发明授权

US5768169A Method and apparatus for improved processing of numeric applications in the presence of subnormal numbers in a computer system 失效
标题翻译：用于在计算机系统中存在次正规数的情况下改进数字应用处理的方法和装置
公开(公告)号：US5768169A
公开(公告)日：1998-06-16
申请号：US537007
申请日：1995-10-02
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F2207/3816
摘要： An apparatus for storing data in a computer memory, the number originating from one of a plurality of floating point data formats. Each data format from which the number originates has a first exponent bias and a minimum exponent value. The number has a first exponent and an unbiased exponent value, the unbiased exponent value equal to the difference between the first exponent and the first exponent bias. The number also has a sign and a significand. The apparatus for storing the number in computer memory consists of at least one sign bit and a significand having an explicit integer bit, the explicit integer bit having a first predetermined value when the number is normal and having a second predetermined value when the number is denormal. The apparatus also has a second exponent with a second exponent bias, the second exponent equal to the sum of the unbiased exponent value and the second exponent bias when the number is normal, the second exponent equal to the sum of the minimum exponent value and the second exponent bias when the number is denormal.
摘要翻译：一种用于将数据存储在计算机存储器中的装置，所述数据源自多个浮点数据格式之一。数字起始的每个数据格式具有第一指数偏差和最小指数值。该数字具有第一指数和无偏指数值，无偏指数值等于第一指数和第一指数偏差之间的差。这个数字也有一个标志和一个有意义的数字。用于存储计算机存储器中的数字的装置由至少一个符号位和具有明显整数位的有效位构成，当数字正常时，该显式整数位具有第一预定值，并且当数字为非正常时具有第二预定值。该装置还具有带有第二指数偏差的第二指数，当数字正常时，第二指数等于无偏指数值和第二指数偏差之和，第二指数等于最小指数值与第二个指数偏差，当数字是不正常的。

10. 发明授权

US06629232B1 Copied register files for data processors having many execution units 失效
标题翻译：具有多个执行单位的数据处理器的复制寄存器文件
公开(公告)号：US06629232B1
公开(公告)日：2003-09-30
申请号：US09609911
申请日：2000-07-03
申请人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
发明人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
IPC分类号： G06F1300
CPC分类号： G06F9/3012 , G06F9/30141 , G06F9/3885 , G06F9/3891
摘要： Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.
摘要翻译：互连主导的大型寄存器文件在芯片面积和延迟时间上都有所减少。具有多个执行单元的处理器中的寄存器文件被分成多个副本。不同的执行单元组可以通过一组本地读写端口读取和写入其自己的文件寄存器副本。所有寄存器文件副本都通过将数据从执行单元写入到寄存器文件的其他副本的至少一些寄存器中的远程写入端口来同步。每个副本可分为本地和全局寄存器。虽然全局寄存器的所有副本仍然由远程写入端口写入，但本地寄存器只能由本地执行单元集群写入。或者或另外，所有执行单元都可以写入其本地寄存器文件副本，但只有一些单元可以将全局寄存器写入寄存器文件的所有副本。

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